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Author:

Guo, Jia (Guo, Jia.) | Yan, Zijin (Yan, Zijin.) | Hou, Ligang (Hou, Ligang.) | Lv, Ang (Lv, Ang.) | Jiang, Nan (Jiang, Nan.)

Indexed by:

CPCI-S

Abstract:

An artificial neural network (ANN) is a parallel, distributed processing system consisting of a large number of interconnected neurons. At present, artificial neural networks have been widely used in signal processing, automation, control systems, image recognition and many other fields. Usually, the realization of neural networks is based on software. However, because the software implementation method cannot achieve real-time calculation in many cases, the hardware implementation method can reflect the inherent parallel processing characteristics of neural networks. This paper proposes an ANN neural network field programmable neuron array based on the design of reusable ANN artificial neural network IP core. It not only can save a lot of hardware resources and improve processing speed, but also has a rapid development cycle and good reconfigurability and other advantages.

Keyword:

Author Community:

  • [ 1 ] [Guo, Jia]Beijing Univ Technol, VLSI & Syst Lab, Beijing 100124, Peoples R China
  • [ 2 ] [Yan, Zijin]Beijing Univ Technol, VLSI & Syst Lab, Beijing 100124, Peoples R China
  • [ 3 ] [Hou, Ligang]Beijing Univ Technol, VLSI & Syst Lab, Beijing 100124, Peoples R China
  • [ 4 ] [Lv, Ang]Beijing Univ Technol, VLSI & Syst Lab, Beijing 100124, Peoples R China
  • [ 5 ] [Jiang, Nan]Beijing Univ Technol, VLSI & Syst Lab, Beijing 100124, Peoples R China

Reprint Author's Address:

  • [Hou, Ligang]Beijing Univ Technol, VLSI & Syst Lab, Beijing 100124, Peoples R China

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Source :

2018 14TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT)

Year: 2018

Page: 1078-1080

Language: English

Cited Count:

WoS CC Cited Count: 0

SCOPUS Cited Count:

ESI Highly Cited Papers on the List: 0 Unfold All

WanFang Cited Count:

Chinese Cited Count:

30 Days PV: 2

Online/Total:1053/10931918
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