This　paper　proposes　a　new　algorithm　to　realize　the　decimal　frequency　divider　with　any　number　divide　ratio.　In　the　statistical　periods,　the　divide　ratio　is　adjusted　dynamically　by　calculating　the　error　of　clock.　Error　of　divider　can　be　reduced,　and　the　accuracy　has　come　to　2.3E-11%　after　4　rounds.　The　implementation　of　decimal　frequency　divider　was　realized　with　FPGA　and　ASIC.　The　article　analyzed　the　resource　and　performance　and　compared　the　result　of　180nm　and　90nm　technology　on　the　ASIC.　The　layout　of　the　circuit　was　realized　on　180nm　technology.　The　experimental　result　indicated　that　the　decimal　frequency　divider　takes　fewer　resources,　and　its　performance　is　steady　and　reliable.