In　the　development　process　of　multi-core　processors,　the　Network　on　Chip　optimizes　the　storage　structure,　but　the　problem　of　＇storage　wall＇　still　exists.　There　are　many　ways　to　alleviate　this　problem.　The　improvement　of　memory　access　performance　can　be　obtained　for　appropriate　address　mapping　between　cache　levels.　As　far　as　the　performance　index　of　address　mapping　is　concerned,　it　can　be　considered　from　the　perspectives　of　memory　access　bandwidth　and　latency　in　different　levels　of　the　storage　system.　Therefore,　a　module-level　detection　tool　is　designed　to　test　the　memory　access　performance.　Based　on　the　hardware　emulation　acceleration　platform,　this　tool　solves　the　online/offline　data　collection　of　memory　access　bandwidth　and　latency.　And　it　implements　the　functions　for　extremely　long　simulation　times,　which　is　data　capture,　analysis,　and　processing.　Under　different　address　mapping　and　data　types　of　different　application　scenarios,　This　tool　tests　memory　access　performance　between　cache　modules.　Based　on　the　data-affinity　address　cross-mapping　method,　this　thesis　proposes　an　address　mapping　optimization　scheme　that　binds　the　directory　controller　unit　and　the　local　memory.　Through　the　module-level　memory　access　performance　test,　the　optimized　data　affinity　and　low-order　address　cross-mapping　method　increases　the　memory　access　bandwidth　by　8%　and　the　maximum　bandwidth　by　9%　when　processing　scheduling-intensive　data.　In　a　word,　this　thesis　establishes　the　memory　access　performance　analysis　method　which　is　＇benchmark　test　program,　module-level　memory　access　performance　detection,　address　mapping　optimization　and　configuration＇.　©　2022　IEEE.