Compressed　sensing　(CS)　theory　has　been　very　popular　since　its　inception　for　its　ability　to　sample　signals　at　the　sub-Nyquist　rate.　However,　the　hardware　implementation　of　the　recovery　algorithm　still　has　much　room　for　improvement.　In　this　paper,　we　propose　a　new　algorithm　named　Half-Candidate　Subspace　Pursuit　(HC-SP)　algorithm　and　a　hardware　structure　based　on　Square-Root-Free　Gram-Schmidt　QR　decomposition　(SRF-GS-QRD)　to　reduce　resource　consumption.　The　functionalities　are　implemented　on　the　Xilinx　Virtex7　FPGA　and　the　results　show　that　our　algorithm　achieved　a　normalized　root　mean　square　error　(NMSE)　of　-100.1dB　with　the　clock　frequency　of　12.5　MHZ.　　©　2022　IEEE.