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Author:

Zhang, M. (Zhang, M..) | Qin, F. (Qin, F..) | Chen, S. (Chen, S..) | Dai, Y.W. (Dai, Y.W..) | Jin, Y.F. (Jin, Y.F..) | Chen, P. (Chen, P..) | An, T. (An, T..) | Gong, Y.P. (Gong, Y.P..)

Indexed by:

EI Scopus SCIE

Abstract:

Annealing process is generally adopted to reduce the residual stress and stabilize the microstructure of TSV-Cu in IC manufacturing. In this paper, the effects of capped Cu layer on the protrusion behaviors of TSV-Cu are investigated considering various double annealing processes. Higher protrusions of TSV-Cu with capped Cu layer are observed compared with that of TSV-Cu without capped Cu layer. The reason is that capped Cu layer impedes the elimination of grain boundaries and local misorientation during the first annealing, resulting in the remaining of larger amounts of atoms and higher energy in the grain boundaries. Thus, it is easier to induce protrusion by grain boundary migration during the second annealing. In addition, the capped Cu layer effects on mechanical properties of TSV-Cu under various double annealing conditions are investigated by nanoindentation test. The values of elastic modulus and hardness are generally higher in the presence of capped Cu layer. The reason is also discussed and clarified. IEEE

Keyword:

protrusion Mechanical factors Through silicon via copper (TSV-Cu) mechanical properties capped Cu layer Annealing Silicon Behavioral sciences Temperature measurement Through-silicon vias microstructure double annealing Microstructure

Author Community:

  • [ 1 ] [Zhang M.]Faculty of Materials and Manufacturing, Institute of Electronics Packaging Technology and Reliability, Beijing University of Technology, Beijing, China
  • [ 2 ] [Qin F.]Faculty of Materials and Manufacturing, Institute of Electronics Packaging Technology and Reliability, Beijing University of Technology, Beijing, China
  • [ 3 ] [Chen S.]Science and Technology on Reliability Physics and Application of Electronic Component Laboratory, China Electronic Product Reliability and Environmental Testing Research Institute, Guangzhou, China
  • [ 4 ] [Dai Y.W.]Faculty of Materials and Manufacturing, Institute of Electronics Packaging Technology and Reliability, Beijing University of Technology, Beijing, China
  • [ 5 ] [Jin Y.F.]Faculty of Materials and Manufacturing, Institute of Electronics Packaging Technology and Reliability, Beijing University of Technology, Beijing, China
  • [ 6 ] [Chen P.]Faculty of Materials and Manufacturing, Institute of Electronics Packaging Technology and Reliability, Beijing University of Technology, Beijing, China
  • [ 7 ] [An T.]Faculty of Materials and Manufacturing, Institute of Electronics Packaging Technology and Reliability, Beijing University of Technology, Beijing, China
  • [ 8 ] [Gong Y.P.]Faculty of Materials and Manufacturing, Institute of Electronics Packaging Technology and Reliability, Beijing University of Technology, Beijing, China

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Source :

IEEE Transactions on Device and Materials Reliability

ISSN: 1530-4388

Year: 2022

Issue: 1

Volume: 23

Page: 1-1

2 . 0

JCR@2022

2 . 0 0 0

JCR@2022

ESI Discipline: ENGINEERING;

ESI HC Threshold:49

JCR Journal Grade:3

CAS Journal Grade:3

Cited Count:

WoS CC Cited Count: 0

SCOPUS Cited Count: 8

ESI Highly Cited Papers on the List: 0 Unfold All

WanFang Cited Count:

Chinese Cited Count:

30 Days PV: 13

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