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Author:

Zhou, R. (Zhou, R..) | An, T. (An, T..) | Qin, F. (Qin, F..) | Gong, Y. (Gong, Y..) | Dai, Y. (Dai, Y..) | Chen, P. (Chen, P..)

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EI Scopus

Abstract:

Press Pack IGBT(PP IGBT) devices often work under high voltage and high current working conditions, and a multi-chip parallel structure is often used inside the PP IGBT device package. In this structure, the multi-chip layout has an important influence on the temperature distribution of chips. In addition, the chip temperature is closely related to the reliability of the PP IGBT device. Therefore, it is of great significance to study the influence of the internal chip layout of the PP IGBT device on the temperature distribution of the chip. In this paper, the finite element model of the PP IGBT device is established, and the electro-thermal coupling simulation is carried out, and simulate the temperature change of each chip inside the device under the condition of power cycle. First, chip temperature distributions were compared for devices containing a single IGBT chip, four IGBT chips and nine IGBT chips. The junction temperature of the chip is shown as a function of time. Then, the influence of the chip separation distance on the temperature was considered, and the chip temperature distribution was compared under the layouts where each chip and the adjacent chips were separated by 2mm and 4mm, respectively. After analyzing the results of the finite element simulation, it is found that due to the close position of the multiple chips connected in parallel inside the PP IGBT device, thermal coupling effect between chips. This coupling effect affects the temperature distribution of the chip and makes the junction temperature higher. And the more chips and the closer the chip distance, the more obvious the effect of this coupling effect on the chip temperature distribution.  © 2022 IEEE.

Keyword:

finite element simulation temperature coupling PP IGBT temperature distribution

Author Community:

  • [ 1 ] [Zhou R.]Beijing University of Technology, Institute of Electronics Packaging Technology and Reliability Beijing, Key Laboratory of Advanced Manufacturing Technology, Faculty of Materials and Manufacturing, Beijing, China
  • [ 2 ] [An T.]Beijing University of Technology, Institute of Electronics Packaging Technology and Reliability Beijing, Key Laboratory of Advanced Manufacturing Technology, Faculty of Materials and Manufacturing, Beijing, China
  • [ 3 ] [Qin F.]Beijing University of Technology, Institute of Electronics Packaging Technology and Reliability Beijing, Key Laboratory of Advanced Manufacturing Technology, Faculty of Materials and Manufacturing, Beijing, China
  • [ 4 ] [Gong Y.]Beijing University of Technology, Institute of Electronics Packaging Technology and Reliability Beijing, Key Laboratory of Advanced Manufacturing Technology, Faculty of Materials and Manufacturing, Beijing, China
  • [ 5 ] [Dai Y.]Beijing University of Technology, Institute of Electronics Packaging Technology and Reliability Beijing, Key Laboratory of Advanced Manufacturing Technology, Faculty of Materials and Manufacturing, Beijing, China
  • [ 6 ] [Chen P.]Beijing University of Technology, Institute of Electronics Packaging Technology and Reliability Beijing, Key Laboratory of Advanced Manufacturing Technology, Faculty of Materials and Manufacturing, Beijing, China

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Year: 2022

Language: English

Cited Count:

WoS CC Cited Count:

SCOPUS Cited Count: 3

ESI Highly Cited Papers on the List: 0 Unfold All

WanFang Cited Count:

Chinese Cited Count:

30 Days PV: 5

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