Multi-core　processors　integrate　with　multiple　computing　units　on　one　chip.　This　technology　is　increasingly　mature,　and　communication　between　cores　has　become　the　largest　research　hotspot.　As　the　number　of　cores　continues　to　increase,　the　humble　bus　structure　can　no　longer　play　the　role　of　multi-core　processors.　Network　on　chip　(NoC)　connects　components　through　routing,　which　greatly　enhances　the　efficiency　of　communication.　However,　the　communication　power　it　consumes　and　network　latency　are　issues　that　cannot　be　ignored.　An　efficient　mapping　algorithm　is　an　effective　method　to　reduce　the　communication　power　and　network　latency.　This　paper　proposes　a　mapping　method.　First,　the　task　is　divided　depending　on　the　scale　of　the　task.　When　the　task　scale　is　small,　to　reduce　the　communication　distance　between　resource　nodes,　a　given　NoC　substructure　is　selected　to　map　the　task;　when　the　task　scale　is　large,　to　reduce　the　communication　between　tasks,　the　tasks　are　clustered　and　tasks　with　dependencies　are　divided　into　the　same　resource　node.　Then　combine　with　an　improving　ant　colony　algorithm　(ACO)　for　mapping.　The　method　proposed　is　being　experimentally　verified　on　NoC　platforms　of　different　scales.　The　experimental　results　show　that　the　method　proposed　is　very　effectual　for　reducing　communication　power　and　network　latency　during　NoC　mapping.