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Author:

Zeng, Q. (Zeng, Q..) | An, T. (An, T..) | Qin, F. (Qin, F..) | Wang, Y. (Wang, Y..)

Indexed by:

CPCI-S EI Scopus

Abstract:

MOSFETs offer a number of benefits relative to traditional power devices. These include a higher switching frequency, higher operating temperature, and higher breakdown voltage. As a result, there has been considerable interest in these devices within the industry. However, alongside this interest, it has become clear that the reliability of MOSFETs is becoming increasingly significant in the research domain. This is because MOSFETs are used in a wide variety of applications in a range of different fields. One of the most significant causes of failure in MOSFET modules is solder layer degradation, which encompasses solder layer delamination and voids. This paper therefore investigates the impact of solder layer voids on the electrical and thermal characteristics of MOSFET modules. Firstly, a simplified finite element model is established, and an electro-thermal simulation analysis is carried out under power cycle conditions. Secondly, finite element models of different defective solder layers are established. The results of the simulations conducted using the aforementioned models are then compared and analyzed. The analysis reveals that the temperature on the chip rises in direct proportion to the increase in defect area, while the current density of the solder layer also increases significantly with the expansion of void area. This provides a certain reference point for the subsequent study of solder degradation. © 2024 IEEE.

Keyword:

FEM MOSFETs Solder layer

Author Community:

  • [ 1 ] [Zeng Q.]Institute of Electronics Packaging Technology and Reliability, Beijing University of Technology, Beijing, China
  • [ 2 ] [An T.]Institute of Electronics Packaging Technology and Reliability, Beijing University of Technology, Beijing, China
  • [ 3 ] [Qin F.]Institute of Electronics Packaging Technology and Reliability, Beijing University of Technology, Beijing, China
  • [ 4 ] [Wang Y.]Institute of Electronics Packaging Technology and Reliability, Beijing University of Technology, Beijing, China

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Year: 2024

Language: English

Cited Count:

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ESI Highly Cited Papers on the List: 0 Unfold All

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Chinese Cited Count:

30 Days PV: 10

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