The　introduction　of　ultralow-k　(ULK)　materials　aims　to　solve　the　back-end-of-line　(BEOL)　resistance　and　capacitance　(RC)　delay,　but　their　higher　porosity　leads　to　lower　fracture　strength.　During　flip　chip　package　integration,　thermo-mechanical　stresses　often　lead　to　cause　chip　package　interaction　(CPI)　induced　reliability　problems　such　as　interlayer　dielectric　(ILD)　cracking　or　delamination.　In　this　paper,　the　stress　and　fracture　behavior　of　ULK　in　BEOL　during　reflow　soldering　of　flip　chip　is　investigated　based　on　the　sub-model　approach.　A　2D　symmetric　global　model　and　a　sub-model　of　Cu/ULK　interconnect　layer　in　BEOL　are　established　using　ABAQUS　software.　First,　sub-model　was　inserted　at　different　locations　of　the　dangerous　bump　to　identify　potential　high　stress　areas.　Then,　fixed　length　cracks　were　inserted　in　BEOL　layers　of　the　sub-model　to　simulate　cracking.　The　J-integral　was　utilized　to　calculate　the　energy　rate　released　(ERR)　at　the　front　edge　of　the　2D　crack.　The　effect　of　Young＇s　modulus　of　ULK　on　ERR　was　also　investigated.　The　results　show　that　the　first　principal　stress　peak　of　ULK　occurs　above　the　edge　of　the　AL　pad　during　reflow　cooling;　the　ERR　at　the　crack　front　edge　gradually　increases　with　the　increasing　number　of　layers;　also,　the　ERR　increases　with　the　increasing　of　the　modulus　of　ULK.　This　study　contributes　to　an　in-depth　understanding　of　the　stress　and　fracture　of　BEOL　in　flip-chips　during　reflow　soldering.　©　2024　IEEE.