MATLAB-Based Performance Verification of 2.4-GHz All-Digital Sub-Sampling PLL with -125 dBc/Hz In-Band Noise - Details

Author：

Xin, Yu (Xin, Yu.) | Lyu, Liding (Lyu, Liding.) | Wan, Peiyuan (Wan, Peiyuan.) | Liu, Xu (Liu, Xu.) | Chen, Zhijie (Chen, Zhijie.)

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Abstract：

This　paper　presents　a　MATLAB　and　Simulink　model　for　a　2.4　GHz　All-Digital　Sub-Sampling　Phase-Locked　Loop　(ADSSPLL)　which　could　meet　the　strict　demands　of　IoT　equipment.　The　proposed　ADSSPLL　uses　Sub-Sampling　Phase　Detectors　(SSPD)　to　replace　the　high-resolution　Time-to-Digital　Converter　(TDC)　and　avoid　using　the　frequency　divider　which　could　greatly　improve　the　in-band　noise　and　reduce　the　loop　complexity.　MATLAB　and　Simulink　tools　are　used　to　verify　the　circuit　performance　of　ADSSPLL.　With　the　reference　frequency　at　50　MHz,　the　In-Band　Noise　is　measured　to　-125　dBc/Hz@1　MHz,　and　it　achieves　a　Root-Mean-Square　(RMS)　output　jitter　of　347　fs.　©　2024　IEEE.

Keyword：

Frequency dividing circuits Biomedical signal processing Signal sampling Computer debugging Phase locked loops Voltage dividers

Author Community：

[ 1 ] [Xin, Yu]College of Microelectronics, Faculty of Information Technology, Beijing University of Technology, Beijing Embedded System Key Lab, Beijing, China
[ 2 ] [Lyu, Liding]College of Microelectronics, Faculty of Information Technology, Beijing University of Technology, Beijing Embedded System Key Lab, Beijing, China
[ 3 ] [Wan, Peiyuan]College of Microelectronics, Faculty of Information Technology, Beijing University of Technology, Beijing Embedded System Key Lab, Beijing, China
[ 4 ] [Liu, Xu]College of Microelectronics, Faculty of Information Technology, Beijing University of Technology, Beijing Embedded System Key Lab, Beijing, China
[ 5 ] [Chen, Zhijie]College of Microelectronics, Faculty of Information Technology, Beijing University of Technology, Beijing Embedded System Key Lab, Beijing, China

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ISSN： 2163-5048

Year： 2024

Page： 139-143

Language： English

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ESI Highly Cited Papers on the List： 0 Unfold All

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30 Days PV： 7

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