A　novel　p-type　Domino　AND　gate　utilizing　the　sleep　transistor,　dual　threshold　voltage,　and　source　following　evaluation　gate　(SEPG)　techniques　is　proposed.　HSPICE　simulation　results　prove　that　the　leakage　current　of　the　proposed　design　can　be　reduced　by　43%,　62%,　and　67%　while　improving　the　noise　margin　3.4%,　23.6%,　and　13.7%　when　compared　to　standard　dual　Vt　Dominos,　standard　low　Vt　dominos,　and　the　SEFG　structure　under　similar　delay　time,　respectively.　Therefore,　the　proposed　Dominos　AND　gate　solves　the　high　leakage　current　and　deteriorated　robustness　problem　in　sub-65　nm　CMOS　technologies.　Finally,　the　inputs　and　clock　signals　combination　sleep　state　dependent　on　leakage　current　characteristics　is　analyzed,　and　the　optimal　sleep　state　is　obtained.