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Abstract：
To optimize the power grid design of a H.264 video decoder chip, the authors put forward the novel algorithm on an auto I/O cell placement (IOAP). The corresponding software is developed, and the experiment is done. The result of H.264 video decoder chip is obvious, and 7.22% of the total length and 16.57% of the routing time is saved. The whole chip＇s performance and design convergence has been improved.
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Journal of Beijing University of Technology
ISSN： 0254-0037
Year： 2006
Issue： 10
Volume： 32
Page： 865-869
Cited Count：
WoS CC Cited Count： 0
SCOPUS Cited Count：
ESI Highly Cited Papers on the List： 0 Unfold All
WanFang Cited Count：
Chinese Cited Count：
30 Days PV： 6
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