Heterogeneous　multi-core　systems　integrate　general　purpose　CPUs　and　data-parallel　GPUs　on　a　single　chip.　However,　the　integration　between　CPUs　and　GPUs　causes　severe　interference　between　CPU　and　GPU　data　traffic.　Because　the　CPUs　and　GPUs　have　diverse　sensitivity　to　network　performance　regarding　latency　and　throughput,　the　Networkon-Chip　(NoC)　needs　to　be　carefully　designed　to　avoid　performance　degradation　caused　by　the　conflicts　between　the　CPUs　and　GPUs.　In　this　paper,　we　propose　an　interference-free　NoC　architecture　to　solve　this　problem.　Specifically,　our　proposed　scheme　can　reduce　the　network　interference　effectively　through　memory　controller　(MC)　partition,　specially　designed　routing　algorithm,　and　a　bypass　scheme　to　reduce　the　cost.　Our　simulation　results　show　that　the　proposed　scheme　can　reduce　over　17%　of　energy　consumption　on　the　average　compared　with　the　baseline　heterogeneous　architecture.　In　addition,　the　average　performance　of　CPUs　can　be　improved　by　as　much　as　30%　and　the　GPU　performance　can　be　increased　over　9%　on　the　average.　©　2020　IEEE.