Utilizing　the　sleep　switch　transistor　technique　and　dual　threshold　voltage　technique,　a　source　following　evaluation　gate　(SEFG)　based　domino　circuit　is　presented　in　this　paper　for　simultaneously　suppressing　the　leakage　current　and　enhancing　noise　immunity.　Simulation　results　show　that　the　leakage　current　of　the　proposed　design　can　be　reduced　by　43%,　62%,　and　67%　while　improving　19.7%,　3.4　%,　and　12.5%　noise　margin　as　compared　to　standard　low　threshold　voltage　circuit,　standard　dual　threshold　voltage　circuit,　and　SEFG　structure,　respectively.　Also,　the　inputs　and　clock　signals　combination　static　state　dependent　leakage　current　characteristic　is　analyzed　and　the　minimum　leakage　states　of　different　domino　AND　gates　are　obtained.　At　last,　the　leakage　power　characteristic　under　process　variations　is　discussed.　©　Springer-Verlag　Berlin　Heidelberg　2011.