Network-on-Chip　(NoC)　has　emerged　as　a　new　design　paradigm　to　the　design　of　on-chip　interconnection　structures　for　system　designers.　However,　such　networks　present　designers　with　a　large　array　of　design　parameters　and　decisions,　many　of　which　are　critical　to　the　efficient　operation　of　NoC　systems.　To　aid　the　design　process　of　complex　systems-on-chip,　this　paper　presents　a　NoC　simulation　environment　for　the　NoC　interconnects　routing　and　application　modeling,　which　has　been　developed　and　implemented　using　SystemC,　a　transaction-level　modeling　language.　The　simulation　environment　provides　substantial　support　to　experiment　with　NoC　design　in　terms　of　routing　algorithms　and　applications　on　different　topologies.　It　is　a　flexible　configurable　environment　which　permits　the　implementation　of　a　wide　range　of　NoC　systems.　An　example　of　network　on　chip　is　constructed　and　simulated　using　the　proposed　simulation　environment　and　the　results　verify　its　modeling　capabilities.　©　2010　IEEE.