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学者姓名：方娟
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Abstract ：
In CPU-GPU heterogeneous systems, there exists intense resource contention between CPUs and GPUs. Traditional resource arbitration policies fail to account for the heterogeneity of cores, leading to inefficient network resource utilization for the CPU, which negatively impacts its performance. In heterogeneous networks, the degree of resource contention varies across different regions. This paper first uses reinforcement learning to analyze the message feature weights relied upon for resource arbitration in different network regions. To achieve more efficient resource allocation, a regional-contention-driven arbitration policy is proposed. The simulation results show that, compared to traditional arbitration policy, the overall network latency is reduced by 7.99%, and CPU performance is improved by 11.42%. Furthermore, a dynamic regional-contention-driven arbitration policy is proposed, which further reduces the overall network latency by 10.47% and increases CPU performance by 16.79% compared to traditional arbitration policy.
Keyword ：
Heterogenous architectures Heterogenous architectures Machine learning Machine learning Network-on-chip (NoC) Network-on-chip (NoC) Arbitration policy Arbitration policy
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| GB/T 7714 | Fang, Juan , Cheng, Haoyu , Wang, Yuening et al. DRCD: a regional-contention-driven arbitration policy for CPU-GPU heterogeneous systems [J]. | JOURNAL OF SUPERCOMPUTING , 2025 , 81 (3) . |
| MLA | Fang, Juan et al. "DRCD: a regional-contention-driven arbitration policy for CPU-GPU heterogeneous systems" . | JOURNAL OF SUPERCOMPUTING 81 . 3 (2025) . |
| APA | Fang, Juan , Cheng, Haoyu , Wang, Yuening , Zhai, Ran . DRCD: a regional-contention-driven arbitration policy for CPU-GPU heterogeneous systems . | JOURNAL OF SUPERCOMPUTING , 2025 , 81 (3) . |
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Abstract ：
Breast cancer is one of the most prevalent cancers among women, with early detection playing a critical role in improving survival rates. This study introduces a novel transformer-based explainable model for breast cancer lesion segmentation (TEBLS), aimed at enhancing the accuracy and interpretability of breast cancer lesion segmentation in medical imaging. TEBLS integrates a multi-scale information fusion approach with a hierarchical vision transformer, capturing both local and global features by leveraging the self-attention mechanism. This model addresses the limitations of existing segmentation methods, such as the inability to effectively capture long-range dependencies and fine-grained semantic information. Additionally, TEBLS incorporates visualization techniques to provide insights into the segmentation process, enhancing the model's interpretability for clinical use. Experiments demonstrate that TEBLS outperforms traditional and existing deep learning-based methods in segmenting complex breast cancer lesions with variations in size, shape, and texture, achieving a mean DSC of 81.86% and a mean AUC of 97.72% on the CBIS-DDSM test set. Our model not only improves segmentation accuracy but also offers a more explainable framework, which has the potential to be used in clinical settings.
Keyword ：
breast cancer lesion segmentation breast cancer lesion segmentation transformer transformer explainable model explainable model
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| GB/T 7714 | Wang, Huina , Wei, Lan , Liu, Bo et al. Transformer-Based Explainable Model for Breast Cancer Lesion Segmentation [J]. | APPLIED SCIENCES-BASEL , 2025 , 15 (3) . |
| MLA | Wang, Huina et al. "Transformer-Based Explainable Model for Breast Cancer Lesion Segmentation" . | APPLIED SCIENCES-BASEL 15 . 3 (2025) . |
| APA | Wang, Huina , Wei, Lan , Liu, Bo , Li, Jianqiang , Li, Jinshu , Fang, Juan et al. Transformer-Based Explainable Model for Breast Cancer Lesion Segmentation . | APPLIED SCIENCES-BASEL , 2025 , 15 (3) . |
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Abstract ：
Modern processors rely on advanced memory management techniques such as predicting and prefetching to bridge the processor-memory gap. However, current mechanisms are primarily designed for a specific memory hierarchy level or access pattern, resulting in inefficiencies for diverse workloads with mixed memory access patterns. To address this challenge, this paper proposes DHCM, a Dynamic Hierarchy Coordination Mechanism that intelligently schedules prediction hierarchies and dynamically optimizes memory access processes to enhance system performance. DHCM integrates a hierarchy coordination mechanism driven by a State Trigger. This mechanism dynamically leverages system feedback to prioritize and coordinate memory operations, enabling the simultaneous management of both off-chip load requests and on-chip cache accesses. Through extensive evaluations on the ChampSim simulator, DHCM demonstrates its adaptability and efficiency with an average IPC improvement of 34.08% and 24.09% on single-core and multi-core systems, respectively. Additionally, DHCM contributes a 64.17% miss coverage and 89.33% DRAM-loads reduction.
Keyword ：
Data prefetcher Data prefetcher Cache Cache Multi-core Multi-core Hardware prefetcher Hardware prefetcher Micro-architecture Micro-architecture
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| GB/T 7714 | Fang, Juan , Li, Jingjing , Teng, Ziyi . Dhcm: a dynamic hierarchy coordination mechanism for memory optimization [J]. | JOURNAL OF SUPERCOMPUTING , 2025 , 81 (5) . |
| MLA | Fang, Juan et al. "Dhcm: a dynamic hierarchy coordination mechanism for memory optimization" . | JOURNAL OF SUPERCOMPUTING 81 . 5 (2025) . |
| APA | Fang, Juan , Li, Jingjing , Teng, Ziyi . Dhcm: a dynamic hierarchy coordination mechanism for memory optimization . | JOURNAL OF SUPERCOMPUTING , 2025 , 81 (5) . |
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Abstract ：
In modern parallel system architectures, prefetchers are essential to mitigating the performance challenges posed by long memory access latencies. These architectures rely heavily on efficient memory access patterns to maximize system throughput and resource utilization. Prefetch aggressiveness is a central parameter in managing these access patterns; although increased prefetch aggressiveness can enhance performance for certain applications, it often risks causing cache pollution and bandwidth contention, leading to significant performance degradation in other workloads. While many existing prefetchers rely on static or simple built-in aggressiveness controllers, a more flexible, adaptive approach based on system-level feedback is essential to achieving optimal performance across parallel computing environments. In this paper, we introduce an Adaptive Prefetch Aggressiveness Control (APAC) framework that leverages Reinforcement Learning (RL) to dynamically manage prefetch aggressiveness in parallel system architectures. The APAC controller operates as an RL agent, which optimizes prefetch aggressiveness by dynamically responding to system feedback on prefetch accuracy, timeliness, and cache pollution. The agent receives a reward signal that reflects the impact of each adjustment on both performance and memory bandwidth, learning to adapt its control strategy based on workload characteristics. This data-driven adaptability makes APAC particularly well-suited for parallel architectures, where efficient resource management across cores is essential to scaling system performance. Our evaluation with the ChampSim simulator demonstrates that APAC effectively adapts to diverse workloads and system configurations, achieving performance gains of 6.73$\%$% in multi-core systems compared to traditional Feedback Directed Prefetching (FDP). By improving memory bandwidth utilization, reducing cache pollution, and minimizing inter-core interference, APAC significantly enhances prefetching performance in multi-core processors. These results underscore APAC's potential as a robust solution for performance optimization in parallel system architectures, where efficient resource management is paramount for scaling modern processing environments.
Keyword ：
Data prefetchers Data prefetchers Accuracy Accuracy prefetcher aggressiveness controller prefetcher aggressiveness controller reinforcement learning reinforcement learning Pollution Pollution Adaptive systems Adaptive systems Bandwidth Bandwidth Systems architecture Systems architecture Random access memory Random access memory Resource management Resource management Prefetching Prefetching memory bandwidth memory bandwidth System performance System performance parallel system architectures parallel system architectures Real-time systems Real-time systems
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| GB/T 7714 | Yang, Huijing , Fang, Juan , Hou, Yumin et al. Reinforcement Learning-Driven Adaptive Prefetch Aggressiveness Control for Enhanced Performance in Parallel System Architectures [J]. | IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS , 2025 , 36 (5) : 977-993 . |
| MLA | Yang, Huijing et al. "Reinforcement Learning-Driven Adaptive Prefetch Aggressiveness Control for Enhanced Performance in Parallel System Architectures" . | IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 36 . 5 (2025) : 977-993 . |
| APA | Yang, Huijing , Fang, Juan , Hou, Yumin , Su, Xing , Xiong, Neal N. . Reinforcement Learning-Driven Adaptive Prefetch Aggressiveness Control for Enhanced Performance in Parallel System Architectures . | IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS , 2025 , 36 (5) , 977-993 . |
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Abstract ：
In cloud data centers, the exponential growth of data places increasing demands on computing, storage, and network resources, especially in multi-tenant environments. While this growth is crucial for ensuring Quality of Service (QoS), it also introduces challenges such as fluctuating resource requirements and static container configurations, which can lead to resource underutilization and high energy consumption. This article addresses online resource provisioning and efficient scheduling for multi-tenant environments, aiming to minimize energy consumption while balancing elasticity and QoS requirements. To address this, we propose a novel optimization framework that reformulates the resource provisioning problem into a more manageable form. By reducing the original multi-constraint optimization to a container placement problem, we apply the interior-point barrier method to simplify the optimization, integrating constraints directly into the objective function for efficient computation. We also introduce elasticity as a key parameter to balance energy consumption with autonomous resource scaling, ensuring that resource consolidation does not compromise system flexibility. The proposed Energy-Efficient and Elastic Resource Provisioning (EEP) framework comprises three main modules: a distributed resource management module that employs vertical partitioning and dynamic leader election for adaptive resource allocation; a prediction module using omega-step prediction for accurate resource demand forecasting; and an elastic scheduling module that dynamically adjusts to tenant scaling needs, optimizing resource allocation and minimizing energy consumption. Extensive experiments across diverse cloud scenarios demonstrate that the EEP framework significantly improves energy efficiency and resource utilization compared to established baselines, supporting sustainable cloud management practices.
Keyword ：
Data centers Data centers Quality of service Quality of service Ions Ions Data center network Data center network Containers Containers energy-efficient energy-efficient resource provisioning resource provisioning Dynamic scheduling Dynamic scheduling QoS QoS Energy consumption Energy consumption Servers Servers Resource management Resource management elastic scheduling elastic scheduling Cloud computing Cloud computing Elasticity Elasticity
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| GB/T 7714 | Lu, Shuaibing , Yan, Ran , Wu, Jie et al. Online Elastic Resource Provisioning With QoS Guarantee in Container-Based Cloud Computing [J]. | IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS , 2025 , 36 (3) : 361-376 . |
| MLA | Lu, Shuaibing et al. "Online Elastic Resource Provisioning With QoS Guarantee in Container-Based Cloud Computing" . | IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 36 . 3 (2025) : 361-376 . |
| APA | Lu, Shuaibing , Yan, Ran , Wu, Jie , Yang, Jackson , Deng, Xinyu , Wu, Shen et al. Online Elastic Resource Provisioning With QoS Guarantee in Container-Based Cloud Computing . | IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS , 2025 , 36 (3) , 361-376 . |
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Abstract ：
With the rapid development of heterogeneous network-on-chip (NoC), a vast amount of shared resources are integrated into NoC. Intense resource competition exists between CPUs and GPUs, leading to congestion and a decrease in overall network performance. Reasonable node placement can minimize network conflicts at the topology level. This paper first discusses the placement of shared last-level cache and memory controller, then selects a more rational placement method and optimizes the path. To solve the hot spots problem in center placement method, a task-based routing algorithm is designed to plan the path. Simulation results demonstrate that, compared to the traditional routing algorithm, the overall network latency is reduced by 9%, and the CPU performance is improved by 13.6%. Furthermore, a dynamic task-based routing algorithm is proposed. Compared to the static task routing algorithm, the overall network latency is reduced by 2.08%, and the CPU performance is improved by 4.09%.
Keyword ：
Routing algorithm Routing algorithm Network-on-chip (NoC) Network-on-chip (NoC) Task-based Task-based Heterogeneous architectures Heterogeneous architectures
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| GB/T 7714 | Fang, Juan , Wei, Zhichao , Liu, Yaqi et al. TB-TBP: a task-based adaptive routing algorithm for network-on-chip in heterogenous CPU-GPU architectures [J]. | JOURNAL OF SUPERCOMPUTING , 2023 , 80 (5) : 6311-6335 . |
| MLA | Fang, Juan et al. "TB-TBP: a task-based adaptive routing algorithm for network-on-chip in heterogenous CPU-GPU architectures" . | JOURNAL OF SUPERCOMPUTING 80 . 5 (2023) : 6311-6335 . |
| APA | Fang, Juan , Wei, Zhichao , Liu, Yaqi , Hou, Yumin . TB-TBP: a task-based adaptive routing algorithm for network-on-chip in heterogenous CPU-GPU architectures . | JOURNAL OF SUPERCOMPUTING , 2023 , 80 (5) , 6311-6335 . |
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Abstract ：
Increasing the number of cores on a chip is one way to solve the bottleneck of exponential growth but an excessive number of cores can lead to problems such as communication blockage and overheating of the chip. Currently, networks-on-chip (NoC) can offer an effective solution to the problem of the communication bottleneck within the chip. With current advancements in IC manufacturing technology, chips can now be 3D-stacked in order to increase chip throughput as well as reduce power consumption while reducing the area of the chip. Automating the mapping of applications into 3D NoC topologies is an important new direction for research in the field of 3D NoC. In this paper, a 3D NoC partitioning algorithm is proposed, which can delineate the 3D NoC region to be mapped. Additionally, a double particle swarm optimization (DPSO) based heuristic algorithm is proposed, which can integrate the characteristics of neighborhood search and genetic algorithms, and thus solve the problem of a particle swarm algorithm falling into local optimal solutions. It is experimentally demonstrated that this DPSO-based hybrid optimization algorithm has a higher throughput rate and lower energy loss than the traditional heuristic algorithm.
Keyword ：
gene cross-mutation gene cross-mutation neighborhood search neighborhood search particle swarm optimization particle swarm optimization 3D NoC 3D NoC high performance computing high performance computing
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| GB/T 7714 | Fang, Juan , Cai, Huayi , Lv, Xin . Hybrid Optimization Algorithm Based on Double Particle Swarm in 3D NoC Mapping [J]. | MICROMACHINES , 2023 , 14 (3) . |
| MLA | Fang, Juan et al. "Hybrid Optimization Algorithm Based on Double Particle Swarm in 3D NoC Mapping" . | MICROMACHINES 14 . 3 (2023) . |
| APA | Fang, Juan , Cai, Huayi , Lv, Xin . Hybrid Optimization Algorithm Based on Double Particle Swarm in 3D NoC Mapping . | MICROMACHINES , 2023 , 14 (3) . |
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Abstract ：
Hardware prefetching and replacement policies are two techniques to improve the performance of the memory subsystem. While prefetching hides memory latency and improves performance, interactions take place with the cache replacement policies, thereby introducing performance variability in the application. To improve the accuracy of reuse of cache blocks in the presence of hardware prefetching, we propose Prefetch-Adaptive Intelligent Cache Replacement Policy (PAIC). PAIC is designed with separate predictors for prefetch and demand requests, and uses machine learning to optimize reuse prediction in the presence of prefetching. By distinguishing reuse predictions for prefetch and demand requests, PAIC can better combine the performance benefits from prefetching and replacement policies. We evaluate PAIC on a set of 27 memory-intensive programs from the SPEC 2006 and SPEC 2017. Under single-core configuration, PAIC improves performance over Least Recently Used (LRU) replacement policy by 37.22%, compared with improvements of 32.93% for Signature-based Hit Predictor (SHiP), 34.56% for Hawkeye, and 34.43% for Glider. Under the four-core configuration, PAIC improves performance over LRU by 20.99%, versus 13.23% for SHiP, 17.89% for Hawkeye and 15.50% for Glider.
Keyword ：
machine learning machine learning Prefetch-Adaptive Intelligent Cache Replacement Policy (PAIC) Prefetch-Adaptive Intelligent Cache Replacement Policy (PAIC) hardware prefetching hardware prefetching replacement policy replacement policy
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| GB/T 7714 | Yang, Hui-Jing , Fang, Juan , Cai, Min et al. A Prefetch-Adaptive Intelligent Cache Replacement Policy Based on Machine Learning [J]. | JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY , 2023 , 38 (2) : 391-404 . |
| MLA | Yang, Hui-Jing et al. "A Prefetch-Adaptive Intelligent Cache Replacement Policy Based on Machine Learning" . | JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY 38 . 2 (2023) : 391-404 . |
| APA | Yang, Hui-Jing , Fang, Juan , Cai, Min , Cai, Zhi . A Prefetch-Adaptive Intelligent Cache Replacement Policy Based on Machine Learning . | JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY , 2023 , 38 (2) , 391-404 . |
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Abstract ：
Normally, threads in a warp do not severely interfere with each other. However, the scheduler must wait until all the threads within complete before scheduling the next warp, resulting in memory divergence. The crux of the problem is scheduling the warp in a more reasonable order. Therefore, we propose a new warp scheduling strategy called WSMP, which is based on multi-level feedback queue (MFQ) and perceptron-based prefetch filtering (PPF). All the warps are sorted beforehand according to the latency tolerance of the warps and pushed into a certain queue in MFQ. We also remold PPF to enhance the modified underlying prefetcher. We are able to strike a balance between cache hit rate and prefetch coverage then. We verify its feasibility using GPGPU-Sim, along with exclusive GPGPU workload. The results show that compared to the baseline, WSMP improves IPC by 26.45% and reduces L2 cache miss rate by 9.54% on average.
Keyword ：
Latency tolerance Latency tolerance Warp scheduling Warp scheduling PPF PPF Multi-level feedback queue Multi-level feedback queue
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| GB/T 7714 | Fang, Juan , Zhao, Li'ang , Cai, Min et al. WSMP: a warp scheduling strategy based on MFQ and PPF [J]. | JOURNAL OF SUPERCOMPUTING , 2023 , 79 (11) : 12317-12340 . |
| MLA | Fang, Juan et al. "WSMP: a warp scheduling strategy based on MFQ and PPF" . | JOURNAL OF SUPERCOMPUTING 79 . 11 (2023) : 12317-12340 . |
| APA | Fang, Juan , Zhao, Li'ang , Cai, Min , Yang, Huijing . WSMP: a warp scheduling strategy based on MFQ and PPF . | JOURNAL OF SUPERCOMPUTING , 2023 , 79 (11) , 12317-12340 . |
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Abstract ：
When multiple central processing unit (CPU) cores and integrated graphics processing units (GPUs) share off-chip main memory, CPU and GPU applications compete for the critical memory resource. This causes serious resource competition and has a negative impact on the overall performance of the system. We describe the competition for shared-memory resources in a CPU-GPU heterogeneous multi-core architecture, and a shared-memory request scheduling strategy based on perceptual and predictive batch-processing is proposed. By sensing the CPU and GPU memory request conditions in the request buffer, the proposed scheduling strategy estimates the GPU latency tolerance and reduces mutual interference between CPU and GPU by processing CPU or GPU memory requests in batches. According to the simulation results, the scheduling strategy improves CPU performance by 8.53% and reduces mutual interference by 10.38% with low hardware complexity.
Keyword ：
Unified memory Unified memory TP391 TP391 CPU-GPU heterogeneous CPU-GPU heterogeneous 9 9 Multi-core Multi-core Access scheduling Access scheduling
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| GB/T 7714 | Fang, Juan , Lin, Sheng , Yang, Huijing et al. A perceptual and predictive batch-processing memory scheduling strategy for a CPU-GPU heterogeneous system [J]. | FRONTIERS OF INFORMATION TECHNOLOGY & ELECTRONIC ENGINEERING , 2023 , 24 (7) : 994-1006 . |
| MLA | Fang, Juan et al. "A perceptual and predictive batch-processing memory scheduling strategy for a CPU-GPU heterogeneous system" . | FRONTIERS OF INFORMATION TECHNOLOGY & ELECTRONIC ENGINEERING 24 . 7 (2023) : 994-1006 . |
| APA | Fang, Juan , Lin, Sheng , Yang, Huijing , Xu, Yixiang , Su, Xing . A perceptual and predictive batch-processing memory scheduling strategy for a CPU-GPU heterogeneous system . | FRONTIERS OF INFORMATION TECHNOLOGY & ELECTRONIC ENGINEERING , 2023 , 24 (7) , 994-1006 . |
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