As　the　demand　expanding　for　high　electrical　performance,　high　pin　count　and　low　cost,　the　copper　pillar　bump　packaging　has　been　extensively　used　in　recent　years.　However,　the　drawback　is　that　copper　pillar　bump　can　introduce　high　stress,　especially　on　low-k　chip.　In　this　paper,　finite　element　method　was　adopted　to　optimize　the　structure　of　copper　pillar　bump,　aiming　at　relieving　the　stress　of　low-k　layer　during　reflow　process　and　improving　the　reliability　of　electronic　packages.　A　strip　finite　element　model　was　established.　Then,　the　copper　pillar　bump　structure　factors,　such　as　the　thickness　of　die,　die　size,　the　diameter　of　copper　pillar　etc.,　were　separately　analyzed　by　finite　element　method.　Taguchi　experiments　were　carried　out　to　analyze　the　significant　structure　factors　which　we　got　before,　and　a　L-27(3(8))　orthogonal　array　was　established.　Finally,　we　got　the　significance　of　these　important　structure　factors　and　their　optimal　combination.