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Author:

Wei, Zikui (Wei, Zikui.) | Peng, Xiaohong (Peng, Xiaohong.) | Wang, Jinhui (Wang, Jinhui.) | Yin, Haibin (Yin, Haibin.) | Gong, Na (Gong, Na.)

Indexed by:

CPCI-S

Abstract:

A novel voltage latched sense amplifier is proposed in this paper. It applies a self-closing bit-line module technique, which makes the input and output nodes separated to optimize sensing delay and power consumption. Initially, the size of transistors in the circuits is adjusted to speed up the circuit and lower the power. The simulation results show that the proposed design improves sensing when smaller bit-lines difference requires for full-swing amplification as the conventional voltage latched sense amplifier. The proposed design also improves power efficiency at least 30% as compared to the conventional voltage latched sense amplifier.

Keyword:

Author Community:

  • [ 1 ] [Wei, Zikui]Beijing Univ Technol, VLSI & Syst Lab, Beijing 100124, Peoples R China
  • [ 2 ] [Peng, Xiaohong]Beijing Univ Technol, VLSI & Syst Lab, Beijing 100124, Peoples R China
  • [ 3 ] [Wang, Jinhui]Beijing Univ Technol, VLSI & Syst Lab, Beijing 100124, Peoples R China
  • [ 4 ] [Yin, Haibin]Beijing Univ Technol, VLSI & Syst Lab, Beijing 100124, Peoples R China
  • [ 5 ] [Gong, Na]North Dakota State Univ, Dept Elect & Comp Engn, Fargo, ND 58102 USA

Reprint Author's Address:

  • [Wang, Jinhui]Beijing Univ Technol, VLSI & Syst Lab, Beijing 100124, Peoples R China

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Source :

2014 12TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT)

Year: 2014

Language: English

Cited Count:

WoS CC Cited Count: 0

SCOPUS Cited Count:

ESI Highly Cited Papers on the List: 0 Unfold All

WanFang Cited Count:

Chinese Cited Count:

30 Days PV: 1

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