A　folding　voltage-to-time　converter　(VTC)　is　proposed　for　time-based　ADC.　Conventional　VTCs　suffer　serious　linearity　interference　due　to　its　large　input　range.　The　proposed　VTC　adopts　a　4x　folding　architecture,　and　thus　reduce　the　VTC　input　range　which　makes　the　gain　of　proposed　VTC　more　larger　and　linear.　The　output　of　a　single　Voltage-to-Time　conversion　is　-110　ps　to　+110　ps　with　the　conversion　gain　of　1.47　ns/V　The　VTC　also　realize　a　process,　voltage,　and　temperature　(PVT)　robustness　by　adjust　the　bias　voltage　of　VTC.　This　work　designed　in　65-nm　CMOS　process　achieves　a　high　linearity　in　a　full　range　of　1.2　Vpp.　©　2021　IEEE.