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Author:

Zhang, Yan (Zhang, Yan.) | Geng, Shuqin (Geng, Shuqin.) | Peng, Xiaohong (Peng, Xiaohong.) | Wang, Zifeng (Wang, Zifeng.) | Tang, Haonan (Tang, Haonan.) | Yan, Shuaiqi (Yan, Shuaiqi.)

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Abstract:

In this paper, we use Python script to read the function detailed description documents of CAN-FD IP, extract the required information according to the main keywords and other information, and automatically generate the qualified System Verilog constrained randomized register configuration stimulator. The simulation results show that the stimulator can meet the design requirements for the configuration of excitation, and can effectively improve the design efficiency of the verification platform. © 2020 IEEE.

Keyword:

Efficiency Excited states Finite difference method High level languages Simulation platform Python

Author Community:

  • [ 1 ] [Zhang, Yan]Vlsi and System Lab, Beijing University of Technology, Beijing, China
  • [ 2 ] [Geng, Shuqin]Vlsi and System Lab, Line 2: Name of Organization Acronyms Acceptable, Beijing, China
  • [ 3 ] [Peng, Xiaohong]Vlsi and System Lab, Beijing University of Technology, Beijing, China
  • [ 4 ] [Wang, Zifeng]Vlsi and System Lab, Beijing University of Technology, Beijing, China
  • [ 5 ] [Tang, Haonan]Vlsi and System Lab, Beijing University of Technology, Beijing, China
  • [ 6 ] [Yan, Shuaiqi]Vlsi and System Lab, Beijing University of Technology, Beijing, China

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Year: 2020

Page: 146-149

Language: English

Cited Count:

WoS CC Cited Count:

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ESI Highly Cited Papers on the List: 0 Unfold All

WanFang Cited Count:

Chinese Cited Count:

30 Days PV: 3

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