The　noise-shaping　(NS)　successive　approximation　register　(SAR)　analog-to-digital　converter　(ADC)　is　an　innovative　hybrid　structure　that　offers　performance　advantages.　The　NS-SAR　ADC　leverages　the　SAR　ADC　as　its　foundation　and　combines　oversampling　technology　and　noise-shaping　technology　found　in　Sigma-Delta　ADC.　This　integration　effectively　combines　the　strengths　of　both　structures　and　enhances　overall　performance.　The　ADC　features　a　simple　circuit　structure,　compact　chip　area,　and　high　energy　efficiency,　which　has　positioned　it　as　a　prominent　research　area.　In　this　paper,　leveraging　the　TSMC　65　nm　GP　process,　the　NS-SAR　ADC　is　designed　with　a　power　supply　voltage　of　1　V.　This　design　adopts　an　8-bit　differential　capacitor　structure,　operates　at　a　sampling　frequency　of　16　MS/s,　and　achieves　an　oversampling　rate　of　16　times　the　desired　performance　indicators.　Through　extensive　circuit　post　simulation　verification,　the　SNR　obtained　reaches　78　dB,　providing　an　effective　bit　resolution　of　12.7　bits.　The　core　chip　area　of　the　ADC　measures　366　x　333　mu　m2,　while　the　power　consumption　is　impressively　low　at　417　mu　W　and　FoMs　is　168　dB.