An efficient clock tree synthesis method with manual hierachical operation - Details

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EI Scopus

Abstract：

A　manual　hierarchical　operation　based　method　for　clock　tree　synthesis　is　described　in　this　paper.　The　implementation　of　this　method　is　adopted　in　a　communication　chip　design　in　a　0.13μm　CMOS.　Comparing　with　the　conventional　clock　tree　synthesis,　the　manual　method　can　obtain　the　following　achievements:　The　clock　cell　area　decreased　by　19%,　hold　time　violations　decreased　by　37%,　and　the　number　of　hold　time　violations　decreased　by　45%,　and　the　clock　skew　was　reduced　by　20%.　©　2018　IEEE.

Keyword：

Forestry Electric clocks Clock distribution networks

Author Community：

[ 1 ] [Li, Jun]Department of Information, Beijing University of Technology, Beijing; 100124, China
[ 2 ] [Wan, Peiyuan]Department of Information, Beijing University of Technology, Beijing; 100124, China
[ 3 ] [Guan, Baolu]Department of Information, Beijing University of Technology, Beijing; 100124, China
[ 4 ] [Su, Limei]Department of Information, Beijing University of Technology, Beijing; 100124, China
[ 5 ] [Ma, Pengyu]Department of Information, Beijing University of Technology, Beijing; 100124, China
[ 6 ] [Chen, Zhijie]Department of Information, Beijing University of Technology, Beijing; 100124, China