An Arithmetic Unit and Multiplying Accumulation Unit of a Custom Floating Point Data Format - Details

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Abstract：

In　this　paper,　a　floating　point　multiplication　and　accumulation　operator　based　on　FPGA　is　designed　for　neural　network　calculation,　and　a　custom　32　bit　floating-point　data　format　is　used　to　change　the　amount　of　computation　by　changing　the　overall　structure　of　the　data,　and　the　performance　of　the　operator　is　optimized.　Finally,　the　simulation　results　in　FPGA　are　given　to　verify　the　correctness　of　the　design.　The　design　saves　the　resources　by　comparing　the　floating　point　operation　with　the　common　algorithm　of　32　bit　floating-point　data　of　the　IEEE　standard.　©　2018　IEEE.

Keyword：

Integrated circuit design Field programmable gate arrays (FPGA) Microsystems IEEE Standards Digital arithmetic Integrated circuits

Author Community：

[ 1 ] [Lv, Ang]Beijing University of Technology, College of Microelectronics, Beijing, China
[ 2 ] [Wang, Chao]Beijing University of Technology, College of Microelectronics, Beijing, China
[ 3 ] [Hou, Ligang]Beijing University of Technology, College of Microelectronics, Beijing, China
[ 4 ] [Zeng, Zhiyong]Beijing University of Technology, College of Microelectronics, Beijing, China
[ 5 ] [Guo, Jia]Beijing University of Technology, College of Microelectronics, Beijing, China
[ 6 ] [Jiang, Nan]Beijing University of Technology, College of Microelectronics, Beijing, China

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Source ：

Year： 2018

Page： 282-285

Language： English

Cited Count：

WoS CC Cited Count：

SCOPUS Cited Count： 1

ESI Highly Cited Papers on the List： 0 Unfold All

WanFang Cited Count：

Chinese Cited Count：

30 Days PV： 10

Affiliated Colleges：

信息科学技术学院本学院/部未明确归属的数据

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