In　this　paper,　a　design　of　memory　built-in　self-test　based　on　JTAG　interface　circuit　applied　in　Power　line　communication　chip　is　implemented　with　SMIC　0.18um　CMOS　1P5M　process.　The　memory　built-in　self-test　circuit　mainly　includes　JTAG　interface　and　memory　test　circuits.　Test　data　and　test　instruction　can　be　sent　and　received　through　only　5　JTAG　interface　pins.　It　can　also　complete　memory　test　with　only　5　instructions　so　that　it　will　save　more　test　cost.　Furthermore,　the　faulty　memory　can　be　positioned　via　the　BIST　controller　and　be　output　through　the　JTAG　port.　The　test　results　show　that　it　can　run　perfectly　with　50MHz　working　clock.　©　2016　IEEE.