A hybrid hierarchical topology and mapping approach oriented to HPCs - Details

Author：

Xiao, C.H. (Xiao, C.H..) | Huang, Z.Q. (Huang, Z.Q..) (Scholars：黄樟钦) | Li, D. (Li, D..) (Scholars：李冬)

Indexed by：

EI Scopus

Abstract：

To　target　the　problems　of　performance,　cost　and　energy　consumption　in　large　scale　communications　of　high　performance　computing,　a　hybrid　hierarchical　topology　and　corresponding　partitioning　approach　are　proposed　in　this　paper.　The　proposed　hierarchical　topology　taking　full　advantages　of　both　traditional　metallic　lines　and　emerging　interconnections　to　implement　one-hop　local　direct　communication　within　the　cluster　and　one-hop　global　high-speed　communication　between　clusters.　The　customized　interconnection　topology　can　be　designed　according　different　applications　through　the　proposed　partitioning　approach　to　get　a　better　trade-off　between　performance　and　cost.　The　case　study　proved　that　the　partitioning　approach　can　implement　the　fast　mapping　from　the　design　to　real　high　performance　computing　system　with　multi-FPGAs,　and　accelerate　the　realization　of　high　performance　reconfigurable　computing　systems.　©　2014　WIT　Press.

Keyword：

Mapping Reconfigurable hardware Topology Economic and social effects Electric network topology Energy utilization Reconfigurable architectures

Author Community：

[ 1 ] [Xiao, C.H.]Embedded Software and System Institution, Beijing University of Technology, Beijing, China
[ 2 ] [Huang, Z.Q.]Embedded Software and System Institution, Beijing University of Technology, Beijing, China
[ 3 ] [Li, D.]Embedded Software and System Institution, Beijing University of Technology, Beijing, China