Design and test of an SRAM chip - Details - 北京工业大学机构库

Author：

Liu, Wenbin (Liu, Wenbin.) | Wang, Jinhui (Wang, Jinhui.) | Hou, Ligang (Hou, Ligang.) | Yang, Hongyan (Yang, Hongyan.) | Kang, Jianbo (Kang, Jianbo.)

Indexed by：

EI Scopus

Abstract：

A　fully　customized　8×8　bits　SRAM　chip,　based　on　Chartered　0.35　um　EEPROM　CMOS　technology,　is　designed　and　taped-out　for　low-power　and　low-cost　electronic　equipment.　According　to　test　results,　when　the　supply　voltage　is　3.3　V　and　clock　frequency　is　20　MHz,　the　chip　can　work　correctly,　and　the　performance　reaches　the　design　specifications,　the　access　time　is　6.2　ns　and　largest　power　consumption　is　6.12　mW.　©　2013　IEEE.

Keyword：

Oscillators (electronic) Static random access storage Integrated circuit design

Author Community：

[ 1 ] [Liu, Wenbin]VLSI and System Lab, Beijing University of Technology, Beijing 100124, China
[ 2 ] [Wang, Jinhui]VLSI and System Lab, Beijing University of Technology, Beijing 100124, China
[ 3 ] [Hou, Ligang]VLSI and System Lab, Beijing University of Technology, Beijing 100124, China
[ 4 ] [Yang, Hongyan]VLSI and System Lab, Beijing University of Technology, Beijing 100124, China
[ 5 ] [Kang, Jianbo]616# Zhongshan West Road, Shijiazhuang, Hebei 051008, China

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Source ：

ISSN： 2162-7541

Year： 2013

Language： English

Cited Count：

WoS CC Cited Count： 0

SCOPUS Cited Count：

ESI Highly Cited Papers on the List： 0 Unfold All

WanFang Cited Count：

Chinese Cited Count：

30 Days PV： 7

Affiliated Colleges：

信息科学技术学院本学院/部未明确归属的数据

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