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Abstract:
To reduce the amount of redundancy caused by the traditional design of power mesh for SOC, a non-uniform ladder type power mesh was proposed in this paper by limiting module place to make sure of the optimized area and optimizing line width to release the routing space. This method could not only effectively reduce the chip area and total length of signal line, but also optimize the power consumption. Based on SMIC 0.18 Eflash 1P4M process, the chip's circuit and layout were designed using Synopsys IC Compiler. After the tape-out and the test, the results show that the chip area reduces by 8.69% and power consumption reduces by 4.04%. This optimized method has some reference for the power mesh design. ©, 2015, NUAA Printing House. All right reserved.
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Research and Progress of Solid State Electronics
ISSN: 1000-3819
Year: 2015
Issue: 2
Volume: 35
Page: 171-175
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ESI Highly Cited Papers on the List: 0 Unfold All
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30 Days PV: 2
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