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学者姓名：陈志杰
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Abstract ：
This letter proposed a coarse-fine two stages time-based analog-to-digital converter (TBADC). The coarse 4-bit TBADC is pipelined with the fine 5-bit TBADC for high conversion rate. There is one bit redundancy to tolerate the gain and offset mismatch between the coarse and fine stages. The residue is transferred by splitting the capacitor array in a fully passive way, which is non-attenuated and consumes less power. The dynamic VTC in this design has a high linearity over a wide input range. The proposed ADC is designed in a 65-nm CMOS technology. It consumed 3.1 mW at 1 GHz and had a Walden figure of merit of 15.9 fJ/conversion step.
Keyword ：
passive passive coarse-fine coarse-fine redundancy redundancy VTC VTC time-domain time-domain ADC ADC
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| GB/T 7714 | Wan, Peiyuan , Bao, Yucheng , Jin, Boyong et al. A 8-bit, 1-GHz coarse-fine time-based ADC with split-CDAC residue transfer [J]. | IEICE ELECTRONICS EXPRESS , 2022 , 19 (7) . |
| MLA | Wan, Peiyuan et al. "A 8-bit, 1-GHz coarse-fine time-based ADC with split-CDAC residue transfer" . | IEICE ELECTRONICS EXPRESS 19 . 7 (2022) . |
| APA | Wan, Peiyuan , Bao, Yucheng , Jin, Boyong , Chen, Zhijie . A 8-bit, 1-GHz coarse-fine time-based ADC with split-CDAC residue transfer . | IEICE ELECTRONICS EXPRESS , 2022 , 19 (7) . |
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Abstract ：
Digital low drop-out regulator (D-LDO) with fast settling time and superior transient response is gaining increasing attention to make up for the deficiency of analog LDO. However, as the traditional digital LDOs regulate the output voltage code at a rate of 1 bit per clock cycle, the transient response speed is limited. In this paper, a multi-bit conversion technique is proposed to improve the transient response speed. The multi-bit conversion technique is achieved by an error detector with adaptive regulation of proportion and integration parameters in the digital controller before pass devices. Besides, a voltage sensor and a time-to-digital converter are employed to convert the output voltage to digital codes. Implemented in a 180-nm CMOS process, the proposed D-LDO features under 36/33 mV of undershoot/overshoot at VOUT = 0.95 V as the load current steps up with 40 mA/1 ns on a 0.5 nF load capacitor. The simulated response time is 0.18-ns, the figure-of-merit of speed FOM1 is 0.65 ps and FOM2 achieves 0.068 pF.
Keyword ：
adaptive control adaptive control embedded power management embedded power management fast response fast response low drop-out regulator low drop-out regulator
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| GB/T 7714 | Lv, Shengping , Wan, Peiyuan , Zhang, Hongda et al. A 0.18-ns Response Time Digital LDO Regulator with Adaptive PI Controller in 180-nm CMOS [J]. | ELECTRONICS , 2021 , 10 (14) . |
| MLA | Lv, Shengping et al. "A 0.18-ns Response Time Digital LDO Regulator with Adaptive PI Controller in 180-nm CMOS" . | ELECTRONICS 10 . 14 (2021) . |
| APA | Lv, Shengping , Wan, Peiyuan , Zhang, Hongda , Geng, Jiarong , Wen, Jiabao , Yao, Yiming et al. A 0.18-ns Response Time Digital LDO Regulator with Adaptive PI Controller in 180-nm CMOS . | ELECTRONICS , 2021 , 10 (14) . |
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Abstract ：
This paper presents a 9-bit 1 GS/s successive approximation register (SAR) analog-to-digital converter (ADC). In this hybrid architecture, the pseudo-pipeline operation is realized, which increases the sampling rate effectively. The ADC adopts two key technologies: the variable gain voltage-to-time converter (VTC), which ensures the linearity is not sacrificed; the segmented time-to-digital converter (STDC), which further improves the linearity of time domain quantization. The prototype ADC is simulated in a standard 65-nm CMOS process with an active area of 0.038 mm(2). The simulated SNDR and SFDR are 44.3 and 58 dB with a sampling rate of 1 GS/s. The FoMW and FoMS are 24.7 fJ/conv-step and 150.7 dB, respectively.
Keyword ：
time-to-digital converter (TDC) time-to-digital converter (TDC) analog-to-digital converter (ADC) analog-to-digital converter (ADC) voltage-to-time converter (VTC) voltage-to-time converter (VTC) high speed high speed hybrid-domain quantization hybrid-domain quantization
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| GB/T 7714 | Bai, Suping , Wan, Zhi , Wan, Peiyuan et al. A 9-Bit 1-GS/s Hybrid-Domain Pseudo-Pipelined SAR ADC Based on Variable Gain VTC and Segmented TDC [J]. | ELECTRONICS , 2021 , 10 (21) . |
| MLA | Bai, Suping et al. "A 9-Bit 1-GS/s Hybrid-Domain Pseudo-Pipelined SAR ADC Based on Variable Gain VTC and Segmented TDC" . | ELECTRONICS 10 . 21 (2021) . |
| APA | Bai, Suping , Wan, Zhi , Wan, Peiyuan , Zhang, Hongda , Ma, Yongkuo , Zhang, Xiaoyu et al. A 9-Bit 1-GS/s Hybrid-Domain Pseudo-Pipelined SAR ADC Based on Variable Gain VTC and Segmented TDC . | ELECTRONICS , 2021 , 10 (21) . |
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Abstract ：
An unity-gain 1-bit flip-around digital-to-analog converter (FADAC), without any capacitor matching issue, is proposed as the front-end input stage in a pipelined analog-to-digital converter (ADC), allowing an input signal voltage swing up to be doubled. This large input swing, coupled with the inherent large feedback factor (ideally beta = 1) of the proposed FADAC, enables a power-efficient low-voltage high-resolution pipelined ADC design. The 1-bit FADAC is exploited in a SHA-less and opamp-sharing pipelined ADC, exhibiting 12-bit resolution with an input swing of 1.8 Vpp under a 1.1 V power supply. Fabricated in a 0.13-mu m CMOS process, the prototype ADC achieves a measured signal-to-noise plus distortion ratio (SNDR) of 66.4 dB and a spurious-free dynamic range (SFDR) of 76.7 dB at 20 MS/s sampling rate. The ADC dissipates 5.2 mW of power and occupies an active area of 0.44 mm(2). The measured differential nonlinearity (DNL) is +0.72/-0.52 least significant bit (LSB) and integral nonlinearity (INL) is +0.84/-0.75 LSB at a 3-MHz sinusoidal input.
Keyword ：
analog-to-digital converter (ADC) analog-to-digital converter (ADC) pipelined ADC pipelined ADC switched capacitor switched capacitor flip-around digital-to-analog converter (FADAC) flip-around digital-to-analog converter (FADAC)
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| GB/T 7714 | Wan, Peiyuan , Su, Limei , Zhang, Hongda et al. A Power-Efficient Pipelined ADC with an Inherent Linear 1-Bit Flip-Around DAC [J]. | ELECTRONICS , 2020 , 9 (1) . |
| MLA | Wan, Peiyuan et al. "A Power-Efficient Pipelined ADC with an Inherent Linear 1-Bit Flip-Around DAC" . | ELECTRONICS 9 . 1 (2020) . |
| APA | Wan, Peiyuan , Su, Limei , Zhang, Hongda , Chen, Zhijie . A Power-Efficient Pipelined ADC with an Inherent Linear 1-Bit Flip-Around DAC . | ELECTRONICS , 2020 , 9 (1) . |
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Abstract ：
The digital low drop-out regulator (LDO) has been used widely in digital circuits for its low supply voltage characteristics. However, as the traditional digital LDOs regulate the output voltage code at a rate of 1 bit per clock cycle, the transient response speed is limited. This paper presents a digital LDO to improve transient response speed with a multi-bit conversion technique. The proposed technology uses a voltage sensor and a time-to-digital converter to convert the output voltage to digital codes. Based on a 65-nm CMOS process, the proposed DLDO reduces the settling time from 147.8 ns to 25.2 ns on average and the response speed is improved by about six times.
Keyword ：
embedded power management embedded power management low drop-out regulator low drop-out regulator fast response fast response digital control digital control
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| GB/T 7714 | Zhang, Hongda , Wan, Peiyuan , Geng, Jiarong et al. A Fast Transient Response Digital LDO with a TDC-Based Signal Converter [J]. | ELECTRONICS , 2020 , 9 (1) . |
| MLA | Zhang, Hongda et al. "A Fast Transient Response Digital LDO with a TDC-Based Signal Converter" . | ELECTRONICS 9 . 1 (2020) . |
| APA | Zhang, Hongda , Wan, Peiyuan , Geng, Jiarong , Liu, Zhaozhe , Chen, Zhijie . A Fast Transient Response Digital LDO with a TDC-Based Signal Converter . | ELECTRONICS , 2020 , 9 (1) . |
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Abstract ：
The digital low dropout regulators are widely used because it can operate at low supply voltage. In the digital low drop-out regulators, the high sampling frequency circuit has a short setup time, but it will produce overshoot, and then the output can be stabilized; although the low sampling frequency circuit output can be directly stabilized, the setup time is too long. This paper proposes a two sampling frequency circuit model, which aims to include the high and low sampling frequencies in the same circuit. By controlling the sampling frequency of the circuit under different conditions, this allows the circuit to combine the advantages of the circuit operating at different sampling frequencies. This shortens the circuit setup time and the stabilization time at the same time. © 2019 IEEE.
Keyword ：
Voltage regulators Voltage regulators Models Models Timing circuits Timing circuits Electric current regulators Electric current regulators
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| GB/T 7714 | Geng, Jiarong , Yu, Baodong , Shen, Chongfei et al. Modeling Digital Low-Dropout Regulator with a Multiple Sampling Frequency Circuit Technology [C] . 2019 : 207-210 . |
| MLA | Geng, Jiarong et al. "Modeling Digital Low-Dropout Regulator with a Multiple Sampling Frequency Circuit Technology" . (2019) : 207-210 . |
| APA | Geng, Jiarong , Yu, Baodong , Shen, Chongfei , Zhang, Hongda , Liu, Zhaozhe , Wan, Peiyuan et al. Modeling Digital Low-Dropout Regulator with a Multiple Sampling Frequency Circuit Technology . (2019) : 207-210 . |
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Abstract ：
The digital low dropout regulators are widely used because it can operate at low supply voltage. In the digital low drop-out regulators, the high sampling frequency circuit has a short setup time, but it will produce overshoot, and then the output can he stabilized; although the low sampling frequency circuit output can be directly stabilized, the setup time is too long. This paper proposes a two sampling frequency circuit model, which aims to include the high and low sampling frequencies in the same circuit. By controlling the sampling frequency of the circuit under different conditions, this allows the circuit to combine the advantages of the circuit operating at different sampling frequencies. This shortens the circuit setup time and the stabilization time at the same time.
Keyword ：
model model setup time setup time multiple sampling frequencies multiple sampling frequencies digital low-dropout regulator digital low-dropout regulator
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| GB/T 7714 | Geng, Jiarong , Yu, Baodong , Shen, Chongfei et al. Modeling Digital Low-Dropout Regulator with a Multiple Sampling Frequency Circuit Technology [C] . 2019 : 207-210 . |
| MLA | Geng, Jiarong et al. "Modeling Digital Low-Dropout Regulator with a Multiple Sampling Frequency Circuit Technology" . (2019) : 207-210 . |
| APA | Geng, Jiarong , Yu, Baodong , Shen, Chongfei , Zhang, Hongda , Liu, Zhaozhe , Wan, Peiyuan et al. Modeling Digital Low-Dropout Regulator with a Multiple Sampling Frequency Circuit Technology . (2019) : 207-210 . |
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Abstract ：
This article proposes a power management circuit for wireless energy, transmission and power supply of wearable devices. As the wearable device becomes smaller and smaller, a power management circuit based on a switched capacitor network and a beta-Multiplier Voltage Reference circuit is designed. The circuit structure of the chip is fabricated by SMIC0.1.8 CMOS process, and its power characteristics and RF signal are analyzed theoretically and experimentally. The operating frequency range of the circuit is 800MHz-1.5GHz, the output voltage of the power supply is stable 1.8V, the total is less than 16 mu w, and it can be effectively controlled by the radio frequency signal.
Keyword ：
Power management Power management wearable device wearable device voltage reference voltage reference charge pump charge pump
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| GB/T 7714 | Mao, Shuaiyu , Wang, Wensi , Liu, Yun et al. Design of Wearable Power Management Circuit with Improved Beta-Multiplier Voltage Reference [C] . 2018 : 240-244 . |
| MLA | Mao, Shuaiyu et al. "Design of Wearable Power Management Circuit with Improved Beta-Multiplier Voltage Reference" . (2018) : 240-244 . |
| APA | Mao, Shuaiyu , Wang, Wensi , Liu, Yun , Chen, Zhijie . Design of Wearable Power Management Circuit with Improved Beta-Multiplier Voltage Reference . (2018) : 240-244 . |
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Abstract ：
The conventional analog-to-digital converter (ADC) with a bypass window for the biomedical applications needs a fine comparator and the transistor size of the fine comparator is smaller than the coarse one, so the mismatch will be large. As a result, this large mismatch will degrade the resolution of the ADC, especially, for the high-resolution applications. A mismatch calibration technique uses the binary capacitance array to reduce the offset voltage of the comparator is introduced in this design. A simulation is implemented in Cadence to evaluate the effect of the calibration technique on the resolution of the ADC. The simulation result shows the offset voltage of dynamic comparator being reduced from 13.93 mV to 3.39 mV (one sigma) and ENOB is improved from 7.68 bits to 10.0 bits by the calibration technique in a 180-nm CMOS technology.
Keyword ：
bypass window bypass window ADC ADC calibration calibration offset offset
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| GB/T 7714 | Liu, Zhaozhe , Wang, Wensi , Wan, Peiyuan et al. An Offset Calibration Technique in a SAR ADC for Biomedical Applications [C] . 2018 : 217-220 . |
| MLA | Liu, Zhaozhe et al. "An Offset Calibration Technique in a SAR ADC for Biomedical Applications" . (2018) : 217-220 . |
| APA | Liu, Zhaozhe , Wang, Wensi , Wan, Peiyuan , Geng, Jiarong , Chen, Zhijie . An Offset Calibration Technique in a SAR ADC for Biomedical Applications . (2018) : 217-220 . |
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Abstract ：
In this paper, a super capacitor charging management integrated circuit (IC) based on reconfigurable photovoltaic cells array is proposed. This IC is based on a novel maximum power point tracking (MPPT) method that arranges photovoltaic (PV) cells into different combination networks in order to optimize the charging efficiency dynamically. With the reconfigurable PV array, various voltage outputs of PV cells charge the super capacitor without inductor based switching regulator. The MPPT circuit is designed according to the I-V characteristics and P-V characteristics of the PV cells. Depending on the charging stage of the super capacitor, different series/parallel combination networks of the PV cells are selected to make the PV cells work in the vicinity of the maximum output power to achieve a higher charging efficiency. Charging current of a single PV ranges from 10 mu A to 100 mu A, the charging efficiency from a small PV cells array to 1F-5V super capacitor can reach more than 80%, up to 94%.
Keyword ：
reconfigurable network reconfigurable network PV cells PV cells photoelectric energy harvesting photoelectric energy harvesting MPPT MPPT
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| GB/T 7714 | Jin, Lu , Wang, Wensi , Yu, Jiaqi et al. Design of Super Capacitor Charging Management Integrated Circuit for Energy Harvesting Based on Reconfigurable Photovoltaic Cells Array [C] . 2018 : 139-143 . |
| MLA | Jin, Lu et al. "Design of Super Capacitor Charging Management Integrated Circuit for Energy Harvesting Based on Reconfigurable Photovoltaic Cells Array" . (2018) : 139-143 . |
| APA | Jin, Lu , Wang, Wensi , Yu, Jiaqi , Chen, Zhijie . Design of Super Capacitor Charging Management Integrated Circuit for Energy Harvesting Based on Reconfigurable Photovoltaic Cells Array . (2018) : 139-143 . |
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