A　power　efficient　BIST　TPG　method　is　proposed　to　reduce　test　power　dissipation　during　scan　testing.　Before　the　test　patterns　are　injected　into　scan　chain,　the　test　set　adopts　a　series　of　preprocessed　strategies　including　don＇t　care　bit　based　2-D　adjusting,　Hamming　Distance　based　2-D　reordering　and　test　cube　matrix　based　two　transpose,　all　steps　will　be　orderly　executed　in　interspersed　way.　The　six　largest　ISCAS＇89　benchmark　circuits　verify　the　proposed　method.　Experimental　results　show　that　the　switching　activities　are　effectively　reduced　when　the　test　set　is　loaded　for　on-chip　scan　testing.　ASDFR　with　MT-filling　scheme　ensures　high　compression　ratio,　the　scan-in　test　power　dissipation　is　further　decreased　by　don＇t　care　bit　based　2-D　adjusting　and　Hamming　Distance　2-D　reordering.　In　addition,　the　BIST　TPG　method　with　less　test　application　time　and　smaller　algorithm　complexity　can　be　widely　applied　to　actual　chip　design　without　adding　extra　decoder　area　overhead.