A　realistic　test　sets　compression　method　is　proposed　to　effectively　reduce　test　data　volume　and　test　application　time　during　system-on-chip　(SoC)　scan　testing,　count　compatible　pattern　run-length　(CCPRL)　coding　method　counts　the　consecutive　number　of　the　equal　to　or　contrary　to　the　retained　patterns,　it　modifies　the　compatible　code　of　variable-length　pattern　run-length　(VPRL)　coding　rules　and　adds　a　count　code　block　to　replace　original　rules　for　increasing　compression　ratio.　Next,　the　decoder　architecture　and　the　state　diagram　of　finite　state　machine　(FSM)　are　designed.　In　addition,　the　power　model　of　test　vectors　is　analyzed,　and　the　power　consumption　of　scanned-in　vectors　is　roughly　evaluated.　The　six　largest　ISCAS＇89　benchmark　circuits　verify　the　proposed　coding　method　has　a　shorter　codeword.　Experiment　results　shows　that　all　compression　ratios　have　been　increased　as　much　as　possible,　test　data　decompression　is