Verification　plays　more　and　more　important　role　in　complex　VLSI　design.　It　has　two　main　challenges:　one　is　to　insure　that　the　input　stimulus　can　control　the　function　spots　inside　the　design;　the　other　is　to　insure　the　errors　can　be　observed　from　the　design　output.　This　paper　presents　an　easy　approach　of　assertion-based　verification　(ABV)　method　by　dividing　it　into　five　steps,　through　which　we　embed　assertions　in　source　codes　to　monitor　key　functional　spots　of　the　design　during　simulation.　As　an　application　example,　a　case　study　of　functional　verification　for　a　UART　model,　using　System　Verilog　Assertion　(SVA),　is　provided.　The　studied　result　shows　that　the　new　method　is　feasible　and　can　be　applied　in　the　design　and　verification　process　to　increase　the　observability　of　the　design.