This　paper　proposes　a　UART　communication　interface　based　on　APB　bus　with　asynchronous　FIFO　buffer.　Based　on　this　design,　the　UART　controller　can　be　flexibly　configured　through　the　AMBA　bus　to　support　baud　rate　modification,　transmission　bits,　configurability　of　parity　mode　and　other　functions.　And　the　asynchronous　FIFO　buffer　function　is　added　for　communication　between　high-speed　devices　and　low-speed　UART　devices.　During　data　transmission,　the　FIFO　can　buffer　the　data　and　the　situation　that　the　UART　device　occupies　the　APB　bus　and　the　processor　for　a　long　time　can　be　avoided,　improving　the　data　transmission　efficiency.　The　design　is　based　on　the　UART　transmission　protocol.　the　finite　state　machine　method　is　used　to　control　the　the　transmission　timing　of　UART　interface,　and　RTL　simulation　and　FPGA　verification　are　carried　out,　showing　good　flexibility　of　this　design.　　©　2022　IEEE.