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Author:

Faraji, Amin (Faraji, Amin.) | Sadrossadat, Sayed Alireza (Sadrossadat, Sayed Alireza.) | Na, Weicong (Na, Weicong.) | Feng, Feng (Feng, Feng.) | Zhang, Qi-Jun (Zhang, Qi-Jun.)

Indexed by:

EI Scopus SCIE

Abstract:

In this paper, for the first time, the deep gated recurrent unit (Deep GRU) is used as a new macromodeling approach for nonlinear circuits. Similar to Long Short-Term Memory (LSTM), the GRU has gating units that control the information flow and makes the network less prone to the vanishing gradient problem. Having a smaller number of gates causes GRU to have fewer parameters compared to LSTM leading to better model accuracy. Using the gates leads gradient formulations to have additive nature which helps them to be more resistant to vanishing and consequently learn long sequences of data. The proposed macromodeling method is capable of modeling nonlinear circuits more accurately and using fewer parameters compared to the conventional LSTM macromodeling method. To further improve the GRU performance, a regularization technique called Gaussian dropout is applied in this paper on deep GRU (GDGRU) to reduce the overfitting problem resulting in better test error. Additionally, the models obtained from the proposed techniques are remarkably faster than the original transistor-level models. To verify the superiority of the proposed method, time-domain modeling of three nonlinear circuits is provided. For these circuits, the comparisons of the accuracy and speed between the conventional recurrent neural network (RNN), the LSTM, and the proposed macromodeling methods are provided.

Keyword:

gated recurrent unit (GRU) Recurrent neural networks Training deep neural network Logic gates Computer-aided design (CAD) macromodeling Neural networks nonlinear circuits Integrated circuit modeling Nonlinear circuits Gaussian dropout Solid modeling recurrent neural network (RNN)

Author Community:

  • [ 1 ] [Faraji, Amin]Yazd Univ, Dept Comp Engn, Yazd 8915818411, Iran
  • [ 2 ] [Sadrossadat, Sayed Alireza]Yazd Univ, Dept Comp Engn, Yazd 8915818411, Iran
  • [ 3 ] [Na, Weicong]Beijing Univ Technol, Fac Informat Technol, Beijing 100124, Peoples R China
  • [ 4 ] [Feng, Feng]Tianjin Univ, Sch Microelect, Tianjin 300072, Peoples R China
  • [ 5 ] [Zhang, Qi-Jun]Carleton Univ, Dept Elect, Ottawa, ON K1S 5B6, Canada

Reprint Author's Address:

  • [Na, Weicong]Beijing Univ Technol, Fac Informat Technol, Beijing 100124, Peoples R China;;

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Source :

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

ISSN: 1549-8328

Year: 2023

Issue: 7

Volume: 70

Page: 2904-2915

5 . 1 0 0

JCR@2022

ESI Discipline: ENGINEERING;

ESI HC Threshold:19

Cited Count:

WoS CC Cited Count: 14

SCOPUS Cited Count: 16

ESI Highly Cited Papers on the List: 0 Unfold All

WanFang Cited Count:

Chinese Cited Count:

30 Days PV: 8

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