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Author:

Zhang, Z. (Zhang, Z..) | Li, Y. (Li, Y..) | Nima, B. (Nima, B..)

Indexed by:

Scopus SCIE

Abstract:

Signal distortion can occur when the gain or attenuation of a component changes non-linearly with frequency, which is referred to as nonlinear frequency response. Common communications components such as filters, amplifiers, and mixers can lead to nonlinear frequency responses, which can cause errors in transmitting and receiving. This article outlines the design and demonstration of a static and dynamic finite impulse response (FIR) digital equalizer circuit. Using predistortion topology with a coupled feedback loop, the adaptive Least-Mean Square (LMS) algorithm was implemented. The FIR filter was simulated in MATLAB and Vivado and then implemented onto an Eclypse Z7 Field Programmable Gate Array (FPGA) evaluation board. Simulations showed that the custom RTL module gave the same frequency response that was produced in MATLAB calculations. The filter was able to dynamically equalize the frequency responses of different nonlinear boards that were used as the devices under test (DUT). Measurements showed that the equalizer was able to compensate for system distortion from 0.2 to 0.8 Nyquist frequency. The phase response remained relatively linear across the band of interest, with a group delay flatness less than 10 ns. © 2023 by the authors.

Keyword:

Least-Mean Square (LMS) optimization algorithm group delay flatness system distortion digital equalizer Field Programmable Gate Array (FPGA) wireless communication MATLAB simulations finite impulse response (FIR) filter predistortion radio frequency (RF) nonlinear frequency response

Author Community:

  • [ 1 ] [Zhang Z.]Department of Electrical and Computer Engineering, University of Alberta, Edmonton, T6G 2R3, AB, Canada
  • [ 2 ] [Li Y.]Department of Electronics and Information Engineering, Beijing-Dublin International College, Beijing University of Technology, Beijing, 100022, China
  • [ 3 ] [Nima B.]Department of Electrical and Computer Engineering, University of Alberta, Edmonton, T6G 2R3, AB, Canada

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Source :

Electronics (Switzerland)

ISSN: 2079-9292

Year: 2023

Issue: 9

Volume: 12

2 . 9 0 0

JCR@2022

ESI Discipline: ENGINEERING;

ESI HC Threshold:19

Cited Count:

WoS CC Cited Count:

SCOPUS Cited Count: 2

ESI Highly Cited Papers on the List: 0 Unfold All

WanFang Cited Count:

Chinese Cited Count:

30 Days PV: 6

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