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Abstract：
In this paper, we analyse the existing C code for the Bayesian deconvolution algorithm, and propose an improved scheme for a CPU platform. The improved algorithm is implemented on an FPGA and functional verification is performed. A complete FPGA hardware acceleration system is then constructed to realize data communication and computation between the FPGA and the upper-level computer. Four-way parallel computation on the FPGA platform is designed and optimized to improve the computational efficiency. The algorithm is implemented through dedicated hardware servers to protect the intellectual property of the software algorithm. © 2023 SPIE.
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ISSN： 0277-786X
Year： 2023
Volume： 12645
Language： English
Cited Count：
WoS CC Cited Count： 0
SCOPUS Cited Count：
ESI Highly Cited Papers on the List： 0 Unfold All
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30 Days PV： 11
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