With　the　rapid　development　of　heterogeneous　network-on-chip　(NoC),　a　large　number　of　shared　resources　are　integrated　on　the　on-chip　networks.　In　a　heterogeneous　CPU-GPU　architecture,　intense　resource　competition　exists　between　CPU　and　GPU.　This　will　cause　congestion　and　decrease　the　overall　performance　of　the　network.　Reasonable　placement　of　network　nodes　can　minimize　network　conflicts　at　the　topology　level.　In　this　paper,　we　first　discuss　the　placement　of　the　shared　last-level-cache　(LLC)　and　memory　controller　(MC)　and　then　choose　a　more　reasonable　placement　method　and　optimize　the　path.　To　solve　the　hot　spots　problem　for　center　placement　method,　a　Task-Based　routing　algorithm　is　designed　to　plan　the　path.　The　simulation　results　show　that,　compared　with　the　basic　dimension-order　XY　routing　algorithm,　the　overall　network　latency　is　reduced　by　9%,　and　the　CPU　performance　is　improved　by　13.6%.　At　the　same　time,　after　allocating　the　proposed　Task-Based-Partition　routing　algorithm　to　virtual　channels,　the　overall　network　latency　is　reduced　by　13.7%,　and　the　CPU　performance　is　improved　by　14.8%.　©　2023　IEEE.