An Analog Neural Computing Unit Circuit Design with 2× 2 MAC Based on CMOS for Storage-Computing Integration - Details

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This　paper　presents　a　Neural　Computing　Unit　(NCU)　design　with　2×　2　analog　multiplier　accumulation　circuit　which　can　achieve　convolution　and　pooling　operations　for　DNN　algorithm.　It　has　the　function　of　integrating　data　storage　and　computation,　which　greatly　improves　energy　efficiency　of　the　chip　for　artificial　intelligence　processors.　Using　180-nm　CMOS　process　technology,　an　analog　neural　computing　unit　circuit　has　been　designed　in　Cadence,　including　a　2×　2　multiplier　accumulation　circuit,　digital　to　analog　convertors,　and　voltage-to-time　converters.　Simulation　results　verify　the　convolution　operation　function.　Meanwhile,　storage-computing　integration　is　also　realized　by　this　circuit.　The　performances　of　the　designed　NCU　have　also　been　evaluated　and　analyzed.　The　error　of　computing　is　within　5%　on　different　corners　and　temperatures.　©　2024　IEEE.

Keyword：

CMOS integrated circuits Integrated circuit design Dividing circuits (arithmetic) Computer circuits Multiplying circuits Digital to analog conversion Analog storage Frequency multiplying circuits Virtual storage

Author Community：

[ 1 ] [Han, Guowei]Beijing University of Technology, Department of Electronic Science and Technology, Beijing, China
[ 2 ] [Chen, Zhuo]Beijing University of Technology, Department of Electronic Science and Technology, Beijing, China
[ 3 ] [Chen, Yunao]Beijing University of Technology, Department of Electronic Science and Technology, Beijing, China
[ 4 ] [Chen, Zhijie]Beijing University of Technology, Department of Electronic Science and Technology, Beijing, China
[ 5 ] [Wan, Peiyuan]Beijing University of Technology, Department of Electronic Science and Technology, Beijing, China
[ 6 ] [Liu, Xu]Beijing University of Technology, Department of Electronic Science and Technology, Beijing, China

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ISSN： 2163-5048

Year： 2024

Page： 92-97

Language： English

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ESI Highly Cited Papers on the List： 0 Unfold All

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30 Days PV： 13

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