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Author:

Wei, Zikui (Wei, Zikui.) | Peng, Xiaohong (Peng, Xiaohong.) | Wang, Jinhui (Wang, Jinhui.) | Yin, Haibin (Yin, Haibin.) | Gong, Na (Gong, Na.)

Indexed by:

EI Scopus

Abstract:

A novel voltage latched sense amplifier is proposed in this paper. It applies a self-closing bit-line module technique, which makes the input and output nodes separated to optimize sensing delay and power consumption. Initially, the size of transistors in the circuits is adjusted to speed up the circuit and lower the power. The simulation results show that the proposed design improves sensing when smaller bit-lines difference requires for full-swing amplification as the conventional voltage latched sense amplifier. The proposed design also improves power efficiency at least 30% as compared to the conventional voltage latched sense amplifier. © 2014 IEEE.

Keyword:

Integrated circuit design CMOS integrated circuits

Author Community:

  • [ 1 ] [Wei, Zikui]VLSI and System Lab, Beijing University of Technology, Beijing; 100124, China
  • [ 2 ] [Peng, Xiaohong]VLSI and System Lab, Beijing University of Technology, Beijing; 100124, China
  • [ 3 ] [Wang, Jinhui]VLSI and System Lab, Beijing University of Technology, Beijing; 100124, China
  • [ 4 ] [Yin, Haibin]VLSI and System Lab, Beijing University of Technology, Beijing; 100124, China
  • [ 5 ] [Gong, Na]Dept. of Electrical and Computer Engineering, North Dakota State University, ND; 58102, United States

Reprint Author's Address:

  • [wang, jinhui]vlsi and system lab, beijing university of technology, beijing; 100124, china

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Source :

Year: 2014

Language: English

Cited Count:

WoS CC Cited Count: 0

SCOPUS Cited Count: 2

ESI Highly Cited Papers on the List: 0 Unfold All

WanFang Cited Count:

Chinese Cited Count:

30 Days PV: 5

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