This　paper　describes　the　basic　principle　of　the　gated　clock.　In　the　system　design　phase,　the　gated　clock　is　added　to　the　RTL　code　for　low-power　design.　Under　TSMC　350　nm　CMOS　process,　Synopsys＇　Design　Compiler,　IC　Compiler,　PT　and　other　tools　were　used　to　complete　the　back-end　physical　implementation.　The　total　power　consumption　of　the　uninserted　gated　clock　is　111.98}\\mathbf{μ　W}$,　the　total　power　consumption　of　the　inserted　gated　clock　is　84.83\μ　W}$,　the　total　power　consumption　is　reduced　by　24.25%,　and　the　area　is　also　reduced.　©　2019　IEEE.