Wavelet neural networks based performance estimation for power gating domino circuits - Details

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EI Scopus

Abstract：

A　system　for　estimating　the　leakage　power,　the　active　power　and　the　delay　of　the　domino　OR　gates　with　the　sleep　transistor　based　on　wavelet　neural　networks　in　45　nm　technology　is　proposed.　By　studying　the　impact　of　the　power　gating　technique　(PGT)　on　the　power　and　delay　characteristics,　the　proposed　model　could　estimate　the　nonlinear　changing　of　the　active　power,　the　leakage　power　and　the　delay　of　the　different　inputs　dynamic　OR　gates　with　fast　speed　convergence　and　high　precision.　The　trend　of　the　estimating　curve　is　discussed.　At　last,　the　comparison　between　the　footer　and　the　header　sleep　transistor　technique　is　given.　©　2009　IEEE.

Keyword：

Leakage currents Timing circuits Transistors Neural networks

Author Community：

[ 1 ] [Wang, Jinhui]VLSI and System Lab, Beijing University of Technology, Beijing 100022, China
[ 2 ] [Wu, Wuchen]VLSI and System Lab, Beijing University of Technology, Beijing 100022, China
[ 3 ] [Gong, Na]College of Electronic and Info Engineering, Hebei University, Baoding, 071002, China
[ 4 ] [Zuo, Lei]VLSI and System Lab, Beijing University of Technology, Beijing 100022, China
[ 5 ] [Peng, Xiaohong]VLSI and System Lab, Beijing University of Technology, Beijing 100022, China
[ 6 ] [Hou, Ligang]VLSI and System Lab, Beijing University of Technology, Beijing 100022, China