A　CMOS　technology　compatible　non-volatile　SRAM　(cNV　SRAM)　is　proposed　in　this　paper　to　achieve　energy　efficient　on-chip　memory.　cNV　SRAM　works　as　conventional　8T　SRAM　to　keep　high　speed　in　work　mode;　in　sleep　mode,　it　backs　up　the　data　in　its　NV　component　and　switches　off　the　power　supply,　thereby　minimizing　the　leakage　energy　without　data　loss.　The　circuit-and　architectural-level　implementation　schemes　of　cNV　SRAM　are　developed　considering　multiple　key　performance　parameters　including　energy　dissipation,　access　time,　write　time,　noise　margin,　layout　area,　restoration　time,　and　injection　charges.　Simulation　results　on　SPEC　2000　benchmark　suite　demonstrate　that　cNV　SRAM　realizes　86　percent　energy　savings　on　average　with　negligible　performance　impact　and　small　hardware　overhead　as　compared　to　conventional　SRAM.　Finally,　the　impact　of　the　sleep　time　and　memory　size　on　the　effectiveness　of　cNV　SRAM　is　analyzed　in　detail　and　it　shows　that　cNV　SRAM　is　particularly　effective　to　implement　large　on-chip　memories　with　long　idle　time.