A low power CMOS technology compatible non-volatile SRAM cell - Details

Author：

Wang, Lina (Wang, Lina.) | Wang, Jinhui (Wang, Jinhui.) | Yang, Zezhong (Yang, Zezhong.) | Hou, Ligang (Hou, Ligang.) | Gong, Na (Gong, Na.)

Indexed by：

EI Scopus

Abstract：

This　paper　presents　a　CMOS　technology　compatible　non-volatile　8T　SRAM　called　NV　SRAM.　NV　SRAM　works　as　conventional　8T　SRAM　to　keep　high　speed　and　high　noise　margin　in　work　mode;　in　sleep　mode,　the　data　is　kept　in　non-volatile　part　and　the　power　supply　is　switched　off,　thereby　minimizing　the　leakage　energy　without　data　loss.　Based　on　65　nm　SMIC　Technology,　simulation　results　show　that　sleep　time　is　longer　than　219　μs,　NV　SRAM　is　able　to　achieve　energy　savings.　The　NV　SRAM　is　particularly　effective　to　implement　on-chip-memories　with　long　idle　time.　©　2014　IEEE.

Keyword：

Static random access storage Energy conservation CMOS integrated circuits

Author Community：

[ 1 ] [Wang, Lina]VLSI and System Lab, Beijing University of Technology, Beijing; 100124, China
[ 2 ] [Wang, Jinhui]VLSI and System Lab, Beijing University of Technology, Beijing; 100124, China
[ 3 ] [Yang, Zezhong]VLSI and System Lab, Beijing University of Technology, Beijing; 100124, China
[ 4 ] [Hou, Ligang]VLSI and System Lab, Beijing University of Technology, Beijing; 100124, China
[ 5 ] [Gong, Na]Dept. of Electrical and Computer Engineering, North Dakota State University, ND; 58102, United States

Reprint Author's Address：

[wang, jinhui]vlsi and system lab, beijing university of technology, beijing; 100124, china

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Source ：

Year： 2014

Language： English

Cited Count：

WoS CC Cited Count： 0

SCOPUS Cited Count： 1

ESI Highly Cited Papers on the List： 0 Unfold All

WanFang Cited Count：

Chinese Cited Count：

30 Days PV： 1

Affiliated Colleges：

信息科学技术学院本学院/部未明确归属的数据

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