A　hybrid　network　technique　is　proposed　in　dynamic　CMOS　XOR/XNOR　gate　to　reduce　the　power　consumption,　save　the　layout　area　and　avoid　signal　skew.　Compared　to　the　standard　N　type　dynamic　gate　with　similar　delay　time,　the　leakage　power,　dynamic　power　and　layout　area　of　the　novel　XOR/XNOR　gate　are　reduced　by　up　to　51%,　13%　and　24%,　respectively.　Also,　the　inputs　and　clock　signals　combination　static　state　dependent　leakage　characteristics　of　three　dynamic　CMOS　XOR/XNOR　gates　are　analyzed　thoroughly.　Finally,　their　robustness　to　noise,　process　and　temperature　variations　are　discussed.　(C)　2011　Elsevier　B.V.　All　rights　reserved.