Through　Silicon　via　(TSV)　technology　makes　the　stacked　chip　to　achieve　the　shortest　distance　of　interconnection　in　vertical　direction　(z　direction).　However,　there　are　many　challenges　for　TSV　wafer　processes.　One　of　the　challenges　is　TSV　wafer　backside　grinding　process.　In　this　paper,　a　predictive　model　was　introduced　to　calculate　the　normal　grinding　force,　and　a　dynamic　finite　element　modeling　methodology　was　established,　and　used　to　study　the　TSV　wafer　stress.　Effects　of　TSV　wafer　thickness,　grinding　wheel　rotation　speed,　and　grinding　wheel　feed　rate　on　the　stress　distribution　were　investigated.