This　paper　proposes　a　novel　10-GS/s　7-bit　time-interleaved　time-domain　Successive　Approximation　Register　(SAR)　Analog-To-Digital　Converter　(ADC)　that　utilizes　a　speed-enhanced　bootstrapped　switch　and　a　triple-latch　comparator.　The　proposed　ADC　comprises　a　4-way　time-domain　ADC　that　employs　the　constant　current　source　charge　Voltage-To-Time　Converter　(VTC)　and　the　7-bit　SAR　Time-To-Digital　Converter　(TDC)　for　medium　resolution　and　high　conversion　speed.　Unlike　conventional　approaches,　an　additional　passive　discharge　path　is　utilized　to　improve　the　settling　time　of　the　switch　while　reducing　the　parasitism　of　the　critical　path.　To　further　enhance　the　ADC　conversion　speed,　the　triple-latch　feed-forward　comparator　operates　in　parallel　to　the　TDC　delay　cell,　eliminating　its　timing　from　the　critical　loop.　The　prototype　was　fabricated　using　a　65nm　CMOS　process,　and　simulation　results　demonstrate　an　SNR　of　40.12　dB　and　an　SFDR　of　50.08　dB　at　a　conversion　rate　of　up　to　10-GS/s　and　input　frequency　up　to　4.41-GS/s.　©　2023　IEEE.