The　low　ionization　rate　of　Mg　acceptors　in　the　p-gallium　nitride　(GaN)　layer　is　a　critical　factor　accounting　for　the　low　current　density　of　E-mode　GaN　p-FETs.　In　this　work,　polarization-enhanced　technology　was　adopted　to　enhance　the　ionization　rate　of　the　p-GaN　channel.　High-performance　recessed-gate　E-mode　GaN　p-FETs　were　fabricated　to　enable　GaN　complementary　logic　(CL)　circuits.　During　fabrication,　the　channel　thickness　(t(x))　is　found　to　be　a　critical　parameter　that　influences　the　device　metrics.　With　a　decrease　in　t(x)　(i.e.,　larger　recess　depth),　a　more　negative　threshold　voltage　(V-th)　is　achieved;　however,　the　trade-off　is　an　increase　in　R-on.　The　E-mode　GaN　p-FET　with　t(x)　=　32　nm　exhibits　a　V-th　of　-1.1　V,　a　high　current　density　of　17.7　mA/mm,　a　high　I-on/I-off　of　6.9　x　10(7),　and　a　low　subthreshold　swing　(SS)　of　93　mV/dec.　Furthermore,　an　E-mode　n-channel　p-GaN　gate　high　electron　mobility　transistor　(HEMT)　was　fabricated　on　the　same　epi-wafer,　exhibiting　a　V-th　of　1.3　V　and　an　R-on　of　6　Omega　&　sdot;mm.　Finally,　a　GaN　CL　inverter　was　fabricated　and　demonstrated　under　V-DD　=　6　V.　Rail-to-rail　voltage　swing　and　low　static　power　consumption　were　both　achieved.　This　work　further　validates　the　feasibility　of　GaN　CL　integrated　circuits　and　power　integrated　circuits　(PICs).