Considering　the　effect　of　temperature　and　process　variations,　the　inputs　and　clock　signals　combination　sleep　state　dependent　leakage　current　characteristics　is　analyzed　and　the　optimal　sleep　state　is　examined　in　sub-65nm　dual　threshold　voltage　(Vt)　footed　domino　circuits.　HSPICE　simulations　based　on　65nm　and　45nm　BSIM4　models　show　that　the　proposed　CLIL　state　(the　clock　signal　and　inputs　are　all　low)　is　the　optimal　state　to　reduce　the　leakage　current　of　the　high　fan-in　footed　domino　circuits　at　high　temperature　and　almost　all　footed　domino　circuits　at　room　temperature,　as　compared　to　the　conventional　CHIL　state　(the　clock　signal　is　high　and　inputs　are　all　low)　and　the　CHIH　state　(the　clock　signal　and　inputs　are　all　high).　Further,　the　influence　of　the　process　variations　on　the　leakage　current　characteristics　of　the　dual　Vt　footed　domino　circuits　is　evaluated.　At　last,　temperature　and　process　variation　aware　new　low　leakage　current　setup　guidelines　are　provided.　©2008　Chinese　Institute　of　Electronics.