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Author:

Wang, Qiang (Wang, Qiang.) | Zhuo, Li (Zhuo, Li.) | Shen, Lan-Sun (Shen, Lan-Sun.)

Indexed by:

EI Scopus PKU CSCD

Abstract:

There is great complexity in H.264 encoder. Therefore, it is difficult to implement an encoder in DSP platform which can run in real-time environment. In this paper, the coding architecture of H.264 Baseline Profile is introduced first, and some reasons for limiting speed are presented according to the analysis of the coding architecture. Besides, several implementation techniques for optimization are presented based on the characteristics of TMS320DM642 chip. The H.264 Baseline Profile encoder is finally real-time implemented based on DSP platform. The testing results demonstrate that encoder has sped up remarkably after optimization, which can meet the real-time encoding requirements for the video sequences with CIF format.

Keyword:

Architecture Image coding Microprocessor chips Optimization Testing Algorithms Digital signal processing Computational complexity

Author Community:

  • [ 1 ] [Wang, Qiang]Signal and Information Processing Lab, Beijing University of Technology, Beijing 100022, China
  • [ 2 ] [Zhuo, Li]Signal and Information Processing Lab, Beijing University of Technology, Beijing 100022, China
  • [ 3 ] [Shen, Lan-Sun]Signal and Information Processing Lab, Beijing University of Technology, Beijing 100022, China

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Source :

Journal of Electronics and Information Technology

ISSN: 1009-5896

Year: 2007

Issue: 12

Volume: 29

Page: 2970-2973

Cited Count:

WoS CC Cited Count: 0

SCOPUS Cited Count:

ESI Highly Cited Papers on the List: 0 Unfold All

WanFang Cited Count:

Chinese Cited Count:

30 Days PV: 11

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