With　the　continuous　development　of　semiconductor　technology,　timing　analysis　is　becoming　more　and　more　complicated.　Static　timing　analysis　is　constantly　improving　the　constraint　mode.　The　traditional　on-chip　variation　(OCV)　has　become　increasingly　unsatisfactory　under　advanced　technology.　The　design　requirements　of　the　tens　of　millions　of　high-speed　chips;　the　advanced　on-chip　methodology　(advanced　OCV,　AOCV),　while　solving　the　pessimism　of　the　traditional　method,　will　increase　the　analysis　time.　This　article　will　introduce　the　new　generation　of　static　timing　analysis　technology　applied　in　the　7Plus　process-Parametric　on-chip　variation　(POCV);　POCV　simulates　the　delay　distribution　probability　obtained　by　the　variation　in　a　certain　case,　which　is　more　accurate　than　AOCV.　And　reduce　the　time　of　timing　analysis,　increasing　the　number　of　iterations　of　timing　analysis.　©　2019　IEEE.