A partition level floorplan method based on data flow analysis for physical design of digital IC - Details

Author：

Zhang, Yinan (Zhang, Yinan.) | Peng, Xiaohong (Peng, Xiaohong.)

Indexed by：

EI Scopus

Abstract：

This　paper　presents　a　partition　level　floorplan　method　for　physical　design　of　digital　integrated　circuit,　which　based　on　data　flow　analysis.　It　uses　Cadence　company　P&R　tool　innovus　to　make　floorplan,　and　takes　a　X86　CPU＇s　south　bridge　design　for　example　to　introduce　how　to　use　this　method　to　guide　floorplan　in　detail.　This　method　is　more　effective　to　improve　the　quality　of　floorplan　for　advanced　process　technology　and　high　speed　IC　design.　©　2017　IEEE.

Keyword：

Microsystems Timing circuits Data flow analysis Integrated circuit design Digital integrated circuits Data transfer

Author Community：

[ 1 ] [Zhang, Yinan]VLSI and System Lab, Beijing University of Technology, Beijing, China
[ 2 ] [Peng, Xiaohong]VLSI and System Lab, Beijing University of Technology, Beijing, China

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Source ：

Year： 2017

Volume： 2017-November

Page： 74-77

Language： English

Cited Count：

WoS CC Cited Count： 0

SCOPUS Cited Count： 6

ESI Highly Cited Papers on the List： 0 Unfold All

WanFang Cited Count：

Chinese Cited Count：

30 Days PV： 9

Affiliated Colleges：

信息科学技术学院本学院/部未明确归属的数据

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